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Sunday, February 7, 2016

Setup and Hold Check: Advance STA (Static Timing Analysis )

Setup and Hold Check

In this series of articles, I will discuss Advance topics related to Setup and Hold Violation. I will try to explain following things
  • How does Timing Tool calculate/report Setup and Hold Violation ?
  • What are the different Reasons for Setup/Hold Violation reported by Timing Tool? Those are Real violation or limitation of tool?
  • Timing Tool take pessimism approach for calculating Setup/Hold violation, How to debug that part before reaching to conclusion that these are real or false Setup/Hold Violation.
  • If there are several Setup/Hold violation, How to narrow down and find out the real cause of the Issue.?
  • What are different methods to fix these violations ?
  • Which approach/Method we should use in which case?

There are list of other questions/confusions, which I will try to cover in this series.
Now, lets start With the same Question "What is setup and Hold Violation?" :)

Basic Circuit of Capture and Launch FlipFlop

Above diagram is very basic Diagram which we always use in STA. In the above diagram,
  • There are 2 Flip flops - FF1 (Launch FF) and FF2 (Capture FF). These Capture and Launch are with respect to Timing path (Path1).
  • 2 Clocks : CLK1 and CLK2 - I assume the ideal one (Means No Skew) for simplicity purpose.
  • There is a small delay between CLK_S (source Clock) and CLK1/CLK2 because of Buffer (Buf2).
  • Every Clock edge is marked with number, so that I can easily refer those number in place of saying "first edge or second edge".
  • Net delay, we are considering Ideal right now.

We know very well that the data launched at Clock Edge "1" by the Launch Flip flop (FF1) is going to capture at Clock edge "2" by the Capture Flip Flop (FF2).
Note: If you don't able to understand this concept, please read the Static Timing Analysis Series.

Setup and Hold Checks are related to Capture Flip Flop. It means we have to understand These concept from the Clock edge at the Capture Flip Flop.
In the below figure,
I took the 2nd Edge of the CLK2 (CLK2 is the capture Clock for Capture FF2), it will help us to understand more clearly.
Data launched by CLK1 (which is associated with Launch FF) at edge "1" is "A" and at edge "2" is "B", which reach at "D2" as per the diagram.
Setup Time and Hold Time of FF2 is marked by Gray and Brown box across the CLK2.

Setup and Hold Time

As per the Setup requirement of FF2 - Data "A" should be stable at "D2", "Setup time" before the "2" clock edge of CLK2.

As per the Hold Requirement of FF2 - Data "A" should be Stable at "D2", "Hold Time" After the "2" Clock Edge of CLK2.
  • There is only one data which can make "A" unstable after the "2" Edge of CLK2 and that's the "B" (which is launched at "2" Edge of CLK1), if it's reaches at "D2" with in the hold time range.
  • So I can also say that data "B" should reach at "D2" only "Hold Time" After the "2" Clock Edge of CLK2.
  • In the above example, "B" is outside the Brown Box (correspond to Hold time), it means "A" will be stable during that time.

And that's the reason,
During the Setup violation - We talk about:
  1. The Same Data: In above example "A".
  2. Two different Clock edges: In above example - "1" of CLK1 (Launched "A") and "2" of CLK2 (Captured "A").
During the Hold Violation - We talk about:
  1. The Same Data: In above example "B".
  2. Same Clock edge: In above example - "2" of CLK1 and CLK2

If "A" is in the Gray box - It's a Setup Violation.
If "B" is in the Brown Box - It's a Hold Violation.

Theoretically, above things looks good but if we are not providing any input data to the design, how come Timing tool figure out what data is launched by CLK1 at "1" or at "2" ? I think you may have this question. If that's the case, how can Timing tool do the calculation for Setup and Hold Violation. :)
Below diagram can help you to understand that part.

Setup and Hold Violation

In the above figure, "A" is the data launched by CLK1 at "1" and "B" is data launched by CLK1 at "2" and diagram shows the time instant when they have reached at D2. Now we are only talking about the Capture Clock CLK2. We have picked 2 edges "2" and "3" (I can also pick "1" and 2" but these edges will help you to understand the concept easily).

If Data "B" reach early (at D2),there are chances that it may come in the Brown Part (of Edge "2") - Means make "A" unstable - That Means Hold Violation in this path.

If Data "B" reach late (at D2), there are chances that it may come in the Red Part (of edge "3") - Means Not stable before Setup Time - That Means Setup Violation in this path.

During the Timing Analysis -
  • Tool know the frequency of Clock - Means Time period - Means It know the Time difference between the 2 Clock Edges. In above example, if "1" is the reference that tool know very well when "2" and "3" will come.
  • How much Time Data will take to travel from Q1 to D2 - depends on the Delay of the circuit. Which Tool know very well.
  • From The Flip Flop Library, it can easily extract the Setup and Hold time.
  • Whether Flip flop is Negative edge triggered or Positive edge triggered, can easily extracted by Flip Flop Library.
  • Other information, Like Net delay, Clock path Skew depends at what stage you are doing the Static Timing analysis and accordingly tool uses those information.
So, in short Timing Tool have all the information which are necessary to do the Timing checks. It don't need the any signal travel information. Analysis result also not going to change if you give input 101 or 010 or 111 or 000 ..etc.

In general, with the help of Time Period, Clock Skew (if it's there), Setup and Hold Time - Timing Tool come up with a window (min and max value) for the Data path Delay.

If Delay is less then the MIN value of that Range - It's a Hold Violation.

If Delay is greater then the Max value of that Range - It's a Setup Violation.

I am sure you are clear what I have tried to explain you. But now you may have few other questions.
  • Delay of a path should be a single value, then why we talk about the max/min delay of a path, maximum delay of data path for Setup check and minimum delay of data path for Hold delay ?
  • As per above explanation, it's very clear that in your circuit for a timing path either there should be a Setup violation or Hold violation. But How come you have seen/heard setup and hold violation at the same time?
I will explain this part in the next coming Articles in more detail.


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