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Tuesday, May 14, 2019

Transmission | Pass Gate - Assignment

Transmission gate or say Pass transistor (NMOS pass transistor and PMOS pass transistor) are one of the concept which is usually asked by Interviewer and most of the time candidates become confused. I will explain the concepts some other time but right now if you know then practice is very important or you should know what all they can ask and how they can twist the questions.

Please try to solve below questions. And prepare yourself for any interview.

Q.1) Implement a Logic Function Y=((A+B)CD)'. Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8.

Q.2) Implement a Logic Function Y=((A' + B'(C' + D' + E' )G' using complementary CMOS. Which input pattern(s) would give the worst and best equivalent pull-down resistance.

Q.3) There is one parameter of an n-channel transistor that is much “better” than the same parameter for the p-channel transistor. This parameter characterizes the major reason why the n-channel transistor offers better performance than the p-channel transistor in circuits using these devices. What is this parameter and how much better is it?

Q.4) Draw the Cross Sectional view of the below given Top View and also tell the device name.

Q.5) Draw the Top view for the given below Cross Sectional view. Define all the layers used in Top view

Q.6) Predict the Vout you can assume VTP as Threshold Voltage of PMOS.

Q.7) Draw an XOR gate using CMOS Structure and using Pass Transistor Logic. Explain the Difference between the two.

Q.8) An NMOS pass-transistor network is supposed to implement logic AND function Y = AB. Please add appropriate signals in the boxes, such that the circuit works properly.

Q.9) An NMOS pass-transistor network is supposed to implement logic OR function Y = A+B. Please add appropriate signals in the boxes (above fig), such that the circuit works properly.

Q.10) Add minimum number of PMOS transistors to the circuit shown below, such that it has a full swing at its output for any combination on its inputs.

  1. For the circuits shown in Fig 1 and Fig 2 the function implemented is same. Is this statement True or False.
  2. If input E arrives last amongst the signal which of the circuit Fig 1 or Fig 2 is more optimized in terms of speed and why?
  3. Which of the circuit will be affected more by body bias Fig 1 or Fig 2 assuming all inputs are arriving at same time

Concepts around these questions and how you are going to analysis - I will discuss and let you know soon.
-Prepared By Niti Gupta
(Director of eLearning and university Program)
(VLSI Expert Private Limited)

-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

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