## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Monday, December 23, 2019

### Latch based Timing Analysis - Part 1

This series we are starting for Latch based Timing Analysis. In case of Latch, there are lot of basic concepts which are similar to Flipflop based Timing but still we get confuse a lot of time, I am going to try my best to clarify that.

Let's first try to understand Flipflop Vs Latch when we are doing Timing analysis. You will see everything is almost same.

In the above circuit you can see that everything is same, only difference - LATCH is placed in place of FLIPFLOP. Apart of this - understanding of Launch Latch and Capture Latch is same.
• Launch Latch - The Latch which is going to launch the data.
• Capture Latch - The Latch which is going to capture the data.
Below comparison also give you understanding between different other terminologies. Like Capture clock path, Launch clock path, Arrival data path, Required path.

Apart of this - remember - all the Timing Terminologies are same in case of Latch. Only difference is the way you are going to apply these concepts. Now, question come why? - because there is a difference in the functionality of the Flipflop and Latch.

Latch is level Triggered and Flipflop is Edge Triggered - this is something everyone know. More specifically - A latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when it is enabled. Latch holds the values of D on Q as Latch become disable. Depending on the polarity of the enable input, Latches are of Positive or Negative level. Flip-flop is an edge-triggered device that changes state at Q as per D on the rising or falling edge of an enable signal. Flipflop holds the values of D until the next respective (rising or falling) edge of the enable signal.

But when I have asked couple of people what will happen in case of Latch at the edges - so either they become confuse or don't have clear understanding. Try to understand this from the following waveform (Launch and Capture clock of latch means - clock which is enable Launch and Capture Latch).

Lets understand this …

Eligibility of Launch Latch (which is Positive level latch) to launch data started the moment there is a rising edge (enable signal making transaction from Negative level to Positive level). It can launch the data continuously (means passing the data from D to Q or say created a continuous path between D and Q) till latch is disabled. This disable activity started at falling edge (the moment enable signal making transaction from Positive Level to Negative level). Now, try to understand the "First edge used for Launch" and "Last edge used for Launch" in the above waveform diagram.

Let's take the example of Data launch at the first edge of the Launch waveform -
1. Data A (red data in above fig) - Delay between the Launch and Capture Latch is very less, then data can be capture at the first positive Level itself at the Capture waveform (as showing in the figure)
• Remember - this is Latch and Latch is transparent at level. In case of Flipflop - data capture only at the edges.
2. Data B (Orange data in above fig) - Delay is significant. Data can reach at D pin of Capture Latch when Latch was disabled. So now, it can only be capture next time when capture Latch is going to enable. Since Data is already present (before the Capture Latch enable), eligibility of capture Latch (which is Positive level latch) to capture data started the moment there is a rising edge (enable signal making transaction from Negative level to Positive level).
• Remember - If you compare this scenario you will find no difference between Latch and Flipflop. Because both are launching the Data at Rising clock edge and both will capture the data at Rising clock edge. :)
3. Data C (green data in the above fig) - Delay is more. It's reaching at D pin of Capture Latch when latch become enable already (second time). Since Latch is already enable, data can easily capture by Latch and passes to Q pin at the same time.
• Remember - If we want that data should be captured by latch at this level only (when capture latch enable second time), then we have to make sure that data should reach at D pin before the Latch disable - means before Falling edge of clock :).
• Remember - If this is the case of Flipflop - then either we have to reduce the delay or we have to make this path as multi-cycle path. But In Latch, still no need of multicycle concept. :)

Now, try to understand the "First edge used for Capture" and "Last edge used for Capture" concept in the above waveform diagram.

If you can understand above diagram, I can say that Latch can start sampling data from the rising edge (or falling edge) itself and continue sampling till the respective falling edge (or rising edge). And Flipflop can only sample the data "at" Rising edge or Negative edge. Both holds the data when they are disable (Latch disable at level and Flipflop disable just after triggering level).

Generally designers prefer flip flops over latches because of this edge-triggered property, which makes their life easy to do analysis and interpretation the design. Latch based design give you a lot of flexibility but remember nothing comes free. You have to pay your TIME and ATTENTION for that. :)

E.g -
1. Latch-based designs are preferred in case of clock frequency in GHz (in high-speed designs). In flip-flop-based high-speed designs, maintaining clock skew is a problem, but latches ease this problem.
2. In the design, slowest path decide the frequency of the design - means at which frequency design can work correctly.
3. Latch based design are more susceptible from process variation.

Now, Lets try to understand below diagram. I am sure, now it's very simple to understand. Different Data are launched between First edge and Last edge used for Launching purpose of X1 level from Launch Latch. As per our expectation, these data should be captured by X2 level at capture Latch (Between first and Last edge used for capturing purpose). If any Data don't reach by the time of Falling edge of Level X2 at capture Latch, we will consider that as not Captured. Now, try to correlate this uncaptured data with Violation of data (what ever we have discussed in Setup and Hold time/violation of Flipflop).

In the next article, we will discuss the Setup/Hold and Delay of Latch. Stay Tuned :)