Lecture1 By IIT Madras:
Lecture2:
An online information center for all who have Interest in Semiconductor Industry.
STA & SI  Chapter1  Chapter2  Chapter3  Chapter4  Chapter5  Chapter6  Chapter7  Chapter8 
Introduction  Static Timing Analysis  Clock  Advance STA  Signal Integrity  EDA Tools  Timing Models  Other Topics 
Extraction & DFM  Chapter1  Chapter2  Chapter3  Chapter4  Chapter5 
Introduction  Parasitic Interconnect Corner (RC Corner)  Manufacturing Effects and Their Modeling  Process Variation  Other Topic 
Reactions: 
Reactions: 
Chapter 1

Chapter 2

Chapter 3

Chapter 4



Introduction


Reactions: 
Chapter 1

Chapter 2

Chapter 3

Chapter 4



Introduction


Reactions: 
A CMOS transistor (or device) has four terminals:
1. Gate ,
2. Source ,
3. Drain ,
4. Bulk ( well , tub , or substrate )
A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals. The transistor source and drain terminals are equivalent as far as digital signals are concerned—we do not worry about labeling an electrical switch with two terminals.
Few Things to remember:
· Logic designers often call the CMOS negative supply VSS or VSS even if it is actually ground or GND. I shall use VSS for the node and V _{SS} for the value.
· CMOS uses positive logic —VDD is logic '1' and VSS is logic '0'.
We turn a transistor on or off using the gate terminal. There are two kinds of CMOS transistors: n channel transistors and p channel transistors. An n channel transistor requires a logic '1' (from now on I’ll just say a '1') on the gate to make the switch conducting (to turn the transistor on ). A p channel transistor requires a logic '0' (again from now on, I’ll just say a '0') on the gate to make the switch nonconducting (to turn the transistor off ). The p channel transistor symbol has a bubble on its gate to remind us that the gate has to be a '0' to turn the transistor on.
If we connect an n channel transistor in series with a p channel transistor, we form an inverter .
With four transistors we can form a twoinput NAND gate.
We can also make a twoinput NOR gate.
The region between source and drain is normally nonconducting. To make an n channel transistor conducting, we must apply a positive voltage V _{GS} (the gate voltage with respect to the source) that is greater than the n channel transistor threshold voltage , V _{t} _{n} (a typical value is 0.5 V and, as far as we are presently concerned, is a constant). This establishes a thin ( Âª 50 Ã…) conducting channel of electrons under the gate. MOS transistors can carry a very small current (the subthreshold current —a few microamperes or less) with V _{GS} <>t _{n} , but we shall ignore this. A transistor can be conducting ( V _{GS} > V _{t} _{n} ) without any current flowing. To make current flow in an n channel transistor we must also apply a positive voltage, V _{DS} , to the drain with respect to the source. For an n channel transistor we must connect the bulk to the most negative potential, GND or VSS, to reverse bias the bulktodrain and bulktosource pn diodes.
The current flowing in the transistor is
current (amperes) = charge (coulombs) per unit time (second). 
We can express the current in terms of the total charge in the channel, Q. If t _{f} (sometimes called the transit time ) is the time that it takes an electron to cross between source and drain, the draintosource current, I _{DSn} , is
We need to find Q and t _{f} . The velocity of the electrons v (a vector) is given by the equation that forms the basis of Ohm’s law:
where m _{n} is the electron mobility ( m _{p} is the hole mobility ) and E is the electric field (with units Vm^{ –1} ).
Typical carrier mobility values are m _{n} = 500–1000 cm^{ 2} V^{ –1} s^{ –1} and m _{p} = 100–400 cm^{ 2} V^{ –1} s^{ –1} . Equation 2.3 is a vector equation, but we shall ignore the vertical electric field and concentrate on the horizontal electric field, E _{x} , that moves the electrons between source and drain. The horizontal component of the electric field is E _{x} = – V _{DS} / L, directed from the drain to the source, where L is the channel length (see Figure 2.3). The electrons travel a distance L with horizontal velocity v _{x} = – m _{n} E _{x} , so that
Next we find the channel charge, Q . The channel and the gate form the plates of a capacitor, separated by an insulator—the gate oxide. We know that the charge on a linear capacitor, C, is Q = C V . Our lower plate, the channel, is not a linear conductor. Charge only appears on the lower plate when the voltage between the gate and the channel, V _{GC} , exceeds the n channel threshold voltage. For our nonlinear capacitor we need to modify the equation for a linear capacitor to the following:
The lower plate of our capacitor is resistive and conducting current, so that the potential in the channel, V _{GC} , varies. In fact, V _{GC} = V _{GS} at the source and V _{GC} = V _{GS} – V _{DS} at the drain. What we really should do is find an expression for the channel charge as a function of channel voltage and sum (integrate) the charge all the way across the channel, from x = 0 (at the source) to x = L (at the drain). Instead we shall assume that the channel voltage, V _{GC} ( x ), is a linear function of distance from the source and take the average value of the charge, which is thus
The gate capacitance, C , is given by the formula for a parallelplate capacitor with length L , width W , and plate separation equal to the gateoxide thickness, T _{ox} . Thus the gate capacitance is
where e_{ ox} is the gateoxide dielectric permittivity. For silicon dioxide, Si0_{ 2} , e_{ ox} Âª 3.45 ¥ 10^{ –11} Fm^{ –1} , so that, for a typical gateoxide thickness of 100 Ã… (1 Ã… = 1 angstrom = 0.1 nm), the gate capacitance per unit area, C_{ ox} Âª 3 f F m m^{ –2} .
Now we can express the channel charge in terms of the transistor parameters,
Q = WL C _{ox} [ ( V _{GS} – V_{ t} _{n} ) – 0.5 V _{DS} ] . 
Finally, the drain–source current is
(W/L) m _{n} C _{ox} [ ( V _{GS} – V_{ t} _{n} ) – 0.5 V _{DS} ] V _{DS}  
(W/L)k^{ '} _{n} [ ( V _{GS} – V_{ t} _{n} ) – 0.5 V _{DS} ] V _{DS} . 
The constant k^{ '} _{n} is the process transconductance parameter (or intrinsic transconductance ):
We also define b _{n} , the transistor gain factor (or just gain factor ) as
The factor W/L (transistor width divided by length) is the transistor shape factor .
Equation 2.9 describes the linear region (or triode region) of operation. This equation is valid until V _{DS} = V _{GS} – V _{t} _{n} and then predicts that I _{DS} decreases with increasing V _{DS} , which does not make physical sense. At V _{DS} = V _{GS} – V _{t} _{n} = V _{DS} _{(sat)} (the saturation voltage ) there is no longer enough voltage between the gate and the drain end of the channel to support any channel charge. Clearly a small amount of charge remains or the current would go to zero, but with very little free charge the channel resistance in a small region close to the drain increases rapidly and any further increase in V _{DS} is dropped over this region. Thus for V _{DS} > V _{GS} – V _{t} _{n} (the saturation region , or pentode region, of operation) the drain current IDS remains approximately constant at the saturation current , I _{DSn} _{(sat)} , where
I _{DSn} _{(sat)} = ( b _{n} /2)( V _{GS} – V_{ t} _{n} )^{ 2} ; V _{GS} > V_{ t} _{n} . 
Figure 2.4 shows the n channel transistor I _{DS} –V _{DS} characteristics for a generic 0.5 m m CMOS process that we shall call G5 . We can fit Eq. 2.12 to the longchannel transistor characteristics (W = 60 m m, L = 6 m m) in Figure 2.4(a). If I _{DSn} _{(sat)} = 2.5 mA (with V _{DS} = 3.0 V, V _{GS} = 3.0 V, V _{t} _{n} = 0.65 V, T _{ox} =100 Ã…), the intrinsic transconductance is
or approximately 90 m AV^{ –2} . This value of k^{ '} _{n} , calculated in the saturation region, will be different (typically lower by a factor of 2 or more) from the value of k^{ '} _{n} measured in the linear region. We assumed the mobility, m _{n} , and the threshold voltage, V_{ t} _{n} , are constants—neither of which is true, as we shall see in Section 2.1.2.
For the p channel transistor in the G5 process, I _{DSp} _{(sat)} = –850 m A ( V _{DS} = –3.0 V, V _{GS} = –3.0 V, V _{t} _{p} = –0.85 V, W = 60 m m, L = 6 m m). Then
PChannel Transistors
The source and drain of CMOS transistors look identical; we have to know which way the current is flowing to distinguish them. The source of an n channel transistor is lower in potential than the drain and vice versa for a p channel transistor. In an n channel transistor the threshold voltage, V _{t} _{n} , is normally positive, and the terminal voltages V _{DS} and V _{GS }are also usually positive. In a p channel transistor V _{t} _{p} is normally negative and we have a choice: We can write everything in terms of the magnitudes of the voltages and currents or we can use negative signs in a consistent fashion.
Here are the equations for a p channel transistor using negative signs:
–k^{ '} _{p} (W/L) [ ( V _{GS} – V_{ t} _{p} ) – 0.5 V _{DS} ] V _{DS} ; V _{DS }> V _{GS} – V_{ t} _{p}  
– b _{p} /2 ( V _{GS} – V_{ t} _{p} )^{ 2} ; V _{DS} <>GS – V_{ t} _{p} . 
In these two equations V _{t} _{p} is negative, and the terminal voltages V _{DS }and V _{GS }are also normally negative The current I _{DSp} is then negative, corresponding to conventional current flowing from source to drain of a p channel transistor (and hence the negative sign for I _{DSp} _{(sat)} in Eq. 2.14).
Velocity Saturation
For a deep submicron transistor, Eq. 2.12 may overestimate the drain–source current by a factor of 2 or more. There are three reasons for this error. First, the threshold voltage is not constant. Second, the actual length of the channel (the electrical or effective length, often written as L eff ) is less than the drawn (mask) length. The third reason is that Eq. 2.3 is not valid for high electric fields. The electrons cannot move any faster than about v max n = 10 5 ms –1 when the electric field is above 10 6 Vm –1 (reached when 1 V is dropped across 1 m m); the electrons become velocity saturated . In this case t f = L eff / v max n , the drain–source saturation current is independent of the transistor length, and Eq. 2.12 becomes
Wv_{ max} _{n} C_{ ox} ( V _{GS} – V_{ t} _{n} ) ; V _{DS} > V _{DS} _{(sat)} (velocity saturated). 
Transistor current is often specified per micron of gate width because of the form of Eq. 2.16. As an example, suppose I _{DSn} _{(sat)} / W = 300 m A m m^{ –1} for the n channel transistors in our G5 process (with V _{DS} = 3.0 V, V _{GS} = 3.0 V, V _{t} _{n} = 0.65 V, L _{eff} = 0.5 m m and T _{ox} = 100 Ã…). Then E _{x} Âª (3 – 0.65) V / 0.5 m m Âª 5 V m m^{ –1} ,
and t _{f} Âª 0.5 m m/37,000 ms^{ –1} Âª 13 ps.
The value for v _{max} _{n} is lower than the 10^{ 5} ms^{ –1} we expected because the carrier velocity is also lowered by mobility degradation due the vertical electric field—which we have ignored. This vertical field forces the carriers to keep “bumping” in to the interface between the silicon and the gate oxide, slowing them down.
Reactions: 