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Friday, December 17, 2010

VLSI basics

Now let talk few thinks about the VLSI basics through few Video.
Lecture1 By IIT Madras:

Lecture 3:

Lecture 4:

Wednesday, September 22, 2010

Conformal Dielectric

Conformal Dielectric

What is the Conformal Dielectric ? It a normal dielectric layer but with certain properties / parameters. Like
  • It surrounds a particular layer which can be either conductor or other dielectric. It means, it is not a general dielectric layer which can present anywhere. You can find it (conformal layer) only at place where it's corresponding layer present. Like POLY, M1 , M2 etc.
  • Definition of conformal layer has at least one of the following parameter (Check below figures for understanding of these parameters)
    • Side Thickness
    • Top Thickness
    • Bottom Thickness

Below diagrams can help you to understand the concept of conformal Dielectric. I am sure no need of any explanation is required after this.

  • Associated Conductor is M1.
  • Side Expand of Dielectric around M1 - Means This Dielectric is Conformal.
  • Top Expand (thickness) of Dielectric Around M1 - Means it's a Conformal Dielectric.
  • Bottom expand (thickness) of Dielectric around M1 - Means It's a Conformal Dielectric.

Note :
  • Associated Conductor is M1.
  • Conformal layer can have above type of structures also where only either "side" or "bottom" or "top" thickness is present.

  • Associated Conductor is M1 for DEL_a1, DEL_b1 and DEL_c1.
  • For other Dielectric (DEL_a2, DEL_a3, DEL_b2, DEL_c2) associated layer is Dielectric. So, these are also Conformal dielectric but around previous dielectric (other Dielectric).
  • Calculation of the Side thickness, bottom thickness and top thickness is as per above figure (when it's associated with other dielectric)but their modelling (in technology file) can vary as per EDA vendor's methodology.

Monday, August 30, 2010

The Difference Between Parasitic Data Formats SPF, DSPF, RSPF, SPEF, and SBPF

Chapter 2: Parasitic Interconnect Corner (RC Corner)
2.1a 2.1b 2.2 2.3 2.4
Basics Of Capacitance and Resistance Interconnect Corners Interconnect Delay Models How to Read SPEF Difference between Parasitic Data Format

The acronyms stand for:
SPF--Standard Parasitic Format
DSPF--Detailed Standard Parasitic Format
RSPF--Reduced Standard Parasitic Format
SPEF--Standard Parasitic Exchange Format
SBPF -- Synopsys Binary Parasitic Format

SPF is a Cadence Design Systems standard for defining netlist parasitic. DSPF and RSPF are the two forms of SPF; the term SPF itself is sometimes used (or misused) to represent parasitic in general. DSPF and RSPF both represent parasitic information as an RC network.

RSPF represents each net as an RC "pi" model, which consists of an equivalent ”near" capacitance at the driver of the net, an equivalent "far" capacitance for the net, and an equivalent resistance connecting these two capacitances. Each net has a single "pi" network for the network, regardless of how many pins are on the net. In addition to the pi network, RSPF causes the PrimeTime tool to calculate an Elmore delay for every pin-to-pin interconnects delay.

In contrast, DSPF models a detailed network of RC parasitic for every net. DSPF is therefore more accurate than RSPF, but DPSF files can be an order of magnitude larger than RSPF files for the same design. In addition, there is no specification for coupling caps in DSPF. DSPF is more similar to a SPICE netlist than the other formats.

SPEF is an Open Verilog Initiative (OVI)--and now IEEE--format for defining netlist parasitic. SPEF is NOT identical to the SPF format, although it is used in a similar manner. Like the SPF format, SPEF includes resistance and capacitance parasitic. Also like the SPF format, SPEF can represent parasitic in detailed or reduced (pi-model) forms, with the reduced form probably being more commonly used. SPEF also has a syntax that allows the modeling of capacitance between different nets, so it is used by the PrimeTime SI (crosstalk) analysis tool. SPEF is smaller than SPF and DSPF because the names are mapped to integers to reduce file size.

SBPF is a Synopsys binary format supported by PrimeTime. Parasitic data converted to this format occupies less disk space and can be read much faster than the same data stored in SPEF format. You can convert parasitics to SBPF, by reading them in and then writing them out with the write_parasitics -format sbpf command.

Note: Reference From

Tuesday, August 24, 2010

How To Read SPEF

Chapter 2: Parasitic Interconnect Corner (RC Corner)
2.1a 2.1b 2.2 2.3 2.4
Basics Of Capacitance and Resistance Interconnect Corners Interconnect Delay Models How to Read SPEF Difference between Parasitic Data Format

SPEF (Standard Parasitic Exchange Format) is documented in chapter 9 of IEEE 1481-1999. Several methods of describing parasitics are documented, but we are discussing only few important one.

General Syntax
A typical SPEF file will have 4 main sections
a header section,
a name map section,
a top level port section and
the main parasitic description section.
Generally, SPEF keywords are preceded with a *. For example, *R_UNIT, *NAME_MAP and *D_NET.
Comments start anywhere on a line with // and run to the end of the line. Each line in a block of comments must start with //.

Header Information
The header section is 14 lines containing information about
the design name,
the parasitic extraction tool,
naming styles
and units.
When reading SPEF, it is important to check the header for units as they vary across tools. By default, SPEF from Astro will be in pF and kOhm while SPEF from Star-RCXT will be in fF and Ohm.

Name Map Section
To reduce file size, SPEF allows long names to be mapped to shorter numbers preceded by a *. This mapping is defined in the name map section. For example:
*509 F_C_EP2
*510 F_C_EP3
*511 F_C_EP4
*512 F_C_EP5
*513 TOP/BUF_ZCLK_2_pin_Z_1
*514 TOP/BUF_ZCLK_3_pin_Z_1
*515 TOP/BUF_ZCLK_4_pin_Z_1
Later in the file, F_C_EP2 can be referred to by its name or by *509. Name mapping in SPEF is not required. Also, mapped and non-mapped names can appear in the same file. Typically, short names such as a pin named A will not be mapped as mapping would not reduce file size. You can write a script will map the numbers back into names. This will make SPEF easier to read, but greatly increase file size.

Port Section
The port section is simply a list of the top level ports in a design. They are also annotated as input, output or bidirect with an I, O or B. For example:
*1 I
*2 I
*3 O
*4 O
*5 O
*6 O
*7 O
*8 B
*9 B

Each extracted net will have a *D_NET section. This will usually consist of a *D_NET line, a *CONN section, a *CAP section, *RES section and a *END line. Single pin nets will not have a *RES section. Nets connected by abutting pins will not have a *CAP section.
*D_NET regcontrol_top/GRC/n13345 1.94482
*I regcontrol_top/GRC/U9743:E I *C 537.855 9150.11 *L 3.70000
*I regcontrol_top/GRC/U9409:A I *C 540.735 9146.02 *L 5.40000
*I regcontrol_top/GRC/U9407:Z O *C 549.370 9149.88 *D OR2M1P
1 regcontrol_top/GRC/U9743:E 0.936057
2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675
3 regcontrol_top/GRC/U9407:Z 0.386093
1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916
2 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9409:A 8.07710
3 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U9407:Z 11.9156
The *D_NET line tells the net name and the net's total capacitance. This capacitance will be the sum of all the capacitances in the *CAP section.

*CONN Section
The *CONN section lists the pins connected to the net. A connection to a cell instance starts with a *I. A connection to a top level port starts with a *P.
The syntax of the *CONN entries is:
*I <pin name> <direction> *C <xy coordinate> <loading or driving information>
The pin name is the name of the pin.
The direction will be I, O or B for input, output or bidirect.
The xy coordinate will be the location of the pin in the layout.
For an input, the loading information will be *L and the pin's capacitance.
For an output, the driving information will be *D and the driving cell's type.
Coordinates for *P port entries may not be accurate because some extraction tools look for the physical location of the logical port (which does not exist) rather then the location of the corresponding pin.

*CAP Section
The *CAP section provides detailed capacitance information for the net. Entries in the *CAP section come in two forms, one for a capacitor lumped to ground and one for a coupled capacitor.
A capacitor lumped to ground has three fields,
an identifying integer,
a node name and
the capacitance value of this node
o 1 regcontrol_top/GRC/U9743:E 0.936057
A coupling capacitor has four fields,
an identifying integer,
two node names and
The values of the coupling capacitor between these two nodes
o 2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675
If netA is coupled to netB, the coupling capacitor will be listed in each net's *CAP section.

*RES Section
The *RES section provides the resistance network for the net.
Entries in *RES section contain 4 fields,
an identifying integer,
two node names and
the resistance between these two nodes.
o 1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916
The resistance network for a net can be very complex. SPEF can contain resistor loops or seemingly ridiculously huge resistors even if the layout is a simple point to point route. This is due how the extraction tool cuts nets into tiny pieces for extraction and then mathematically stitches them back together when writing SPEF.

Parasitic Values
The above examples show a single parasitic value for each capacitor or resistor. It is up to the parasitic extraction and delay calculation flow to decide which corner this value represents. SPEF also allows for min:typ:max values to be reported:
1 regcontrol_top/GRC/U9743:E 0.936057:1.02342:1.31343
The IEEE standard requires either 1 or 3 values to be reported. However, some tools will report min:max pairs and it is expected that tools may report many corners (corner1:corner2:corner3:corner4) in the future.

Monday, August 23, 2010


A CMOS transistor (or device) has four terminals:

1. Gate ,

2. Source ,

3. Drain ,

4. Bulk ( well , tub , or substrate )

A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals. The transistor source and drain terminals are equivalent as far as digital signals are concerned—we do not worry about labeling an electrical switch with two terminals.

Few Things to remember:

· Logic designers often call the CMOS negative supply VSS or VSS even if it is actually ground or GND. I shall use VSS for the node and V SS for the value.

· CMOS uses positive logic —VDD is logic '1' and VSS is logic '0'.

We turn a transistor on or off using the gate terminal. There are two kinds of CMOS transistors: n -channel transistors and p -channel transistors. An n -channel transistor requires a logic '1' (from now on I’ll just say a '1') on the gate to make the switch conducting (to turn the transistor on ). A p -channel transistor requires a logic '0' (again from now on, I’ll just say a '0') on the gate to make the switch nonconducting (to turn the transistor off ). The p -channel transistor symbol has a bubble on its gate to remind us that the gate has to be a '0' to turn the transistor on.

If we connect an n -channel transistor in series with a p -channel transistor, we form an inverter .

With four transistors we can form a two-input NAND gate.

We can also make a two-input NOR gate.

The region between source and drain is normally nonconducting. To make an n -channel transistor conducting, we must apply a positive voltage V GS (the gate voltage with respect to the source) that is greater than the n -channel transistor threshold voltage , V t n (a typical value is 0.5 V and, as far as we are presently concerned, is a constant). This establishes a thin ( ª 50 Å) conducting channel of electrons under the gate. MOS transistors can carry a very small current (the subthreshold current —a few microamperes or less) with V GS <>t n , but we shall ignore this. A transistor can be conducting ( V GS > V t n ) without any current flowing. To make current flow in an n -channel transistor we must also apply a positive voltage, V DS , to the drain with respect to the source. For an n -channel transistor we must connect the bulk to the most negative potential, GND or VSS, to reverse bias the bulk-to-drain and bulk-to-source pn -diodes.

The current flowing in the transistor is

current (amperes) = charge (coulombs) per unit time (second).


We can express the current in terms of the total charge in the channel, Q. If t f (sometimes called the transit time ) is the time that it takes an electron to cross between source and drain, the drain-to-source current, I DSn , is

I DSn = Q / t f .


We need to find Q and t f . The velocity of the electrons v (a vector) is given by the equation that forms the basis of Ohm’s law:

v = – m n E ,


where m n is the electron mobility ( m p is the hole mobility ) and E is the electric field (with units Vm –1 ).

Typical carrier mobility values are m n = 500–1000 cm 2 V –1 s –1 and m p = 100–400 cm 2 V –1 s –1 . Equation 2.3 is a vector equation, but we shall ignore the vertical electric field and concentrate on the horizontal electric field, E x , that moves the electrons between source and drain. The horizontal component of the electric field is E x = – V DS / L, directed from the drain to the source, where L is the channel length (see Figure 2.3). The electrons travel a distance L with horizontal velocity v x = – m n E x , so that


L 2

t f







v x

m n V DS

Next we find the channel charge, Q . The channel and the gate form the plates of a capacitor, separated by an insulator—the gate oxide. We know that the charge on a linear capacitor, C, is Q = C V . Our lower plate, the channel, is not a linear conductor. Charge only appears on the lower plate when the voltage between the gate and the channel, V GC , exceeds the n -channel threshold voltage. For our nonlinear capacitor we need to modify the equation for a linear capacitor to the following:

Q = C ( V GC – V t n ) .


The lower plate of our capacitor is resistive and conducting current, so that the potential in the channel, V GC , varies. In fact, V GC = V GS at the source and V GC = V GS – V DS at the drain. What we really should do is find an expression for the channel charge as a function of channel voltage and sum (integrate) the charge all the way across the channel, from x = 0 (at the source) to x = L (at the drain). Instead we shall assume that the channel voltage, V GC ( x ), is a linear function of distance from the source and take the average value of the charge, which is thus

Q = C [ ( V GS – V t n ) – 0.5 V DS ] .


The gate capacitance, C , is given by the formula for a parallel-plate capacitor with length L , width W , and plate separation equal to the gate-oxide thickness, T ox . Thus the gate capacitance is

WL e ox





WLC ox



T ox

where e ox is the gate-oxide dielectric permittivity. For silicon dioxide, Si0 2 , e ox ª 3.45 ¥ 10 –11 Fm –1 , so that, for a typical gate-oxide thickness of 100 Å (1 Å = 1 angstrom = 0.1 nm), the gate capacitance per unit area, C ox ª 3 f F m m –2 .

Now we can express the channel charge in terms of the transistor parameters,

Q = WL C ox [ ( V GS – V t n ) – 0.5 V DS ] .


Finally, the drain–source current is



Q/ t f


(W/L) m n C ox [ ( V GS – V t n ) – 0.5 V DS ] V DS


(W/L)k ' n [ ( V GS – V t n ) – 0.5 V DS ] V DS .


The constant k ' n is the process transconductance parameter (or intrinsic transconductance ):

k ' n = m n C ox .


We also define b n , the transistor gain factor (or just gain factor ) as

b n = k ' n (W/L) .


The factor W/L (transistor width divided by length) is the transistor shape factor .

Equation 2.9 describes the linear region (or triode region) of operation. This equation is valid until V DS = V GS – V t n and then predicts that I DS decreases with increasing V DS , which does not make physical sense. At V DS = V GS – V t n = V DS (sat) (the saturation voltage ) there is no longer enough voltage between the gate and the drain end of the channel to support any channel charge. Clearly a small amount of charge remains or the current would go to zero, but with very little free charge the channel resistance in a small region close to the drain increases rapidly and any further increase in V DS is dropped over this region. Thus for V DS > V GS – V t n (the saturation region , or pentode region, of operation) the drain current IDS remains approximately constant at the saturation current , I DSn (sat) , where

I DSn (sat) = ( b n /2)( V GS – V t n ) 2 ; V GS > V t n .


Figure 2.4 shows the n -channel transistor I DS –V DS characteristics for a generic 0.5 m m CMOS process that we shall call G5 . We can fit Eq. 2.12 to the long-channel transistor characteristics (W = 60 m m, L = 6 m m) in Figure 2.4(a). If I DSn (sat) = 2.5 mA (with V DS = 3.0 V, V GS = 3.0 V, V t n = 0.65 V, T ox =100 Å), the intrinsic transconductance is

2(L/W) I DSn (sat)

k ' n




( V GS – V t n ) 2

2 (6/60) (2.5 ¥ 10 –3 )



(3.0 – 0.65) 2


9.05 ¥ 10 –5 AV –2

or approximately 90 m AV –2 . This value of k ' n , calculated in the saturation region, will be different (typically lower by a factor of 2 or more) from the value of k ' n measured in the linear region. We assumed the mobility, m n , and the threshold voltage, V t n , are constants—neither of which is true, as we shall see in Section 2.1.2.

For the p -channel transistor in the G5 process, I DSp (sat) = –850 m A ( V DS = –3.0 V, V GS = –3.0 V, V t p = –0.85 V, W = 60 m m, L = 6 m m). Then

2 (L/W) (– I DSp (sat) )

k ' p




( V GS – V t p ) 2

2 (6/60) (850 ¥ 10 –6 )



(–3.0 – (–0.85) ) 2


3.68 ¥ 10 –5 AV –2

P-Channel Transistors

The source and drain of CMOS transistors look identical; we have to know which way the current is flowing to distinguish them. The source of an n -channel transistor is lower in potential than the drain and vice versa for a p -channel transistor. In an n -channel transistor the threshold voltage, V t n , is normally positive, and the terminal voltages V DS and V GS are also usually positive. In a p -channel transistor V t p is normally negative and we have a choice: We can write everything in terms of the magnitudes of the voltages and currents or we can use negative signs in a consistent fashion.

Here are the equations for a p -channel transistor using negative signs:



–k ' p (W/L) [ ( V GS – V t p ) – 0.5 V DS ] V DS ; V DS > V GS – V t p


I DSp (sat)


– b p /2 ( V GS – V t p ) 2 ; V DS <>GS – V t p .

In these two equations V t p is negative, and the terminal voltages V DS and V GS are also normally negative The current I DSp is then negative, corresponding to conventional current flowing from source to drain of a p -channel transistor (and hence the negative sign for I DSp (sat) in Eq. 2.14).

Velocity Saturation

For a deep submicron transistor, Eq. 2.12 may overestimate the drain–source current by a factor of 2 or more. There are three reasons for this error. First, the threshold voltage is not constant. Second, the actual length of the channel (the electrical or effective length, often written as L eff ) is less than the drawn (mask) length. The third reason is that Eq. 2.3 is not valid for high electric fields. The electrons cannot move any faster than about v max n = 10 5 ms –1 when the electric field is above 10 6 Vm –1 (reached when 1 V is dropped across 1 m m); the electrons become velocity saturated . In this case t f = L eff / v max n , the drain–source saturation current is independent of the transistor length, and Eq. 2.12 becomes

I DSn (sat)


Wv max n C ox ( V GS – V t n ) ; V DS > V DS (sat) (velocity saturated).


Transistor current is often specified per micron of gate width because of the form of Eq. 2.16. As an example, suppose I DSn (sat) / W = 300 m A m m –1 for the n -channel transistors in our G5 process (with V DS = 3.0 V, V GS = 3.0 V, V t n = 0.65 V, L eff = 0.5 m m and T ox = 100 Å). Then E x ª (3 – 0.65) V / 0.5 m m ª 5 V m m –1 ,

I DSn (sat) /W

v max n




C ox ( V GS – V t n )

(300 ¥ 10 –6 ) (1 ¥ 10 6 )



(3.45 ¥ 10 –3 ) (3 – 0.65)


37,000 ms –1

and t f ª 0.5 m m/37,000 ms –1 ª 13 ps.

The value for v max n is lower than the 10 5 ms –1 we expected because the carrier velocity is also lowered by mobility degradation due the vertical electric field—which we have ignored. This vertical field forces the carriers to keep “bumping” in to the interface between the silicon and the gate oxide, slowing them down.

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