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Monday, December 26, 2016

UNATE : Timing Arc



Previous Article is all about "What is Timing Arc?" and "How can you categorize them (Net Arc and Gate Arc; Delay Arc and Constraint Arc)?"
But still we need to understand how timing arc help us to answer our questions related to any Standard Cell or any Flip-flop or any system (like Macros, IPs)...
  1. For a Particular Input (Rising or falling), What type of Output (output is rising or falling or no change) you get ?
  2. How much time (may be in the form of Delay) it will take to respond for a particular Input ?
  3. Is there any constraint on any pin and if yes, then what are those and on what pin ?

First Question can be Answer if we know: How Input pin is logically connected with Output pin.

What is the meaning of Logically connection? It Means, what is going to happen “For Rising Input"...whether Output
  • Fall or
  • Rise or
  • No Change

Timing Arc help us to identify this with a property known as Unate.

UNATE


Unate are of three types:


  • Positive Unate:
    • Rising Input – Rising Output OR No change in Output.
      • If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No change".
    • Falling Input – Falling Output OR No change in Output
      • If we apply Faling signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No change".
    • E.g:
      • BUFFER
      • AND gate (will explain this in detail later below)
      • OR gate (will explain this in detail later below)
  • Negative Unate:
    • Rising Input – Falling Output OR No change in Output.
      • If we apply rising signal to the input of a Timing Arc, corresponding output signal is either Falling or there is "No change".
    • Falling Input – Rising Output OR No change in Output
      • If we apply Falling signal to the input of a Timing Arc, corresponding output signal is either Rising or there is "No change".
    • E.g:
      • Inverter (NOT gate)
      • NAND gate (will explain this in detail later below)
      • NOR gate (will explain this in detail later below)
  • Non_Unate:
    • The non-unate represents a function where change in output value cannot be determined from the direction of the change in the input value. Output pin value is not dependent on single Input Pin. It also depends on 2nd Input pin. Since Timing arc will be between the Single Input and Single Output pin, so it’s difficult to identify this relationship directly.
    • E.g:
      • XOR gate (will explain this in detail later below)
      • XNOR gate (will explain this in detail later below)

Buffer:

In the Buffer there is one input pin and one output pin. Behavior of Buffer we all know.
  • Rising Input results Rising Output.
  • Falling Input results Falling Output.

So, Timing Arc between Input and Output pin of Buffer are Positive Unate.

Remember, there are 2 Timing arcs in Buffer: One for Rising Edge and other for Falling edge.

Inverter:

In the NOT Gate (Inverter) there is one input pin and one output pin. Behavior of Inverter also we know very well.
  • Rising Input results Falling Output.
  • Falling Input results Rising Output.

So, Timing Arc between Input and Output pin of Inverter are Negative Unate.

Remember, there are 2 Timing arcs in Inverter: One for Rising Edge and other for Falling edge.

AND Gate:

Above is the "Truth Table" of AND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 0)
A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 0)
B = 1 , A (0-> 1) ; Y - Changes from 0-> 1


In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 0)
A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - No change (constant at 0)
B = 1 , A (1-> 0) ; Y - Change from 1-> 0


So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in AND gate:
  1. Input Pin A to Output Pin Y for Rising Edge
  2. Input Pin A to Output Pin Y for Falling Edge
  3. Input Pin B to Output Pin Y for Rising Edge
  4. Input Pin B to Output Pin Y for Falling Edge


OR Gate:


Above is the "Truth Table" of OR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1
A = 1 , B (0-> 1) ; Y - No change (constant at 1)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1
B = 1 , A (0-> 1) ; Y - No change (constant at 1)


In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0
A = 1 , B (1-> 0) ; Y - No change (constant at 1)
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - No change (constant at 1)


So, in both the cases - Timing arc between A-Y and B-Y is Positive Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in OR gate:
  1. Input Pin A to Output Pin Y for Rising Edge
  2. Input Pin A to Output Pin Y for Falling Edge
  3. Input Pin B to Output Pin Y for Rising Edge
  4. Input Pin B to Output Pin Y for Falling Edge


NAND Gate:


Above is the "Truth Table" of NAND gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - No change (constant at 1)
A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - No change (constant at 1)
B = 1 , A (0-> 1) ; Y - Changes from 1-> 0


In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - No change (constant at 1)
A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - No change (constant at 1)
B = 1 , A (1-> 0) ; Y - Change from 0-> 1


So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NAND gate:
  1. Input Pin A to Output Pin Y for Rising Edge
  2. Input Pin A to Output Pin Y for Falling Edge
  3. Input Pin B to Output Pin Y for Rising Edge
  4. Input Pin B to Output Pin Y for Falling Edge


NOR Gate:


Above is the "Truth Table" of NOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0
A = 1 , B (0-> 1) ; Y - No change (constant at 0)

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
B = 1 , A (0-> 1) ; Y - No change (constant at 0)


In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1
A = 1 , B (1-> 0) ; Y - No change (constant at 0)
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - No change (constant at 0)


So, in both the cases - Timing arc between A-Y and B-Y is Negative Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in NOR gate:
  1. Input Pin A to Output Pin Y for Rising Edge
  2. Input Pin A to Output Pin Y for Falling Edge
  3. Input Pin B to Output Pin Y for Rising Edge
  4. Input Pin B to Output Pin Y for Falling Edge


XOR Gate:


Above is the "Truth Table" of XOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 0-> 1
A = 1 , B (0-> 1) ; Y - Changes from 1-> 0

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 0-> 1
B = 1 , A (0-> 1) ; Y - Changes from 1-> 0


In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 1-> 0
A = 1 , B (1-> 0) ; Y - Change from 0-> 1
B = 0 , A (1-> 0) ; Y - Change from 1-> 0
B = 1 , A (1-> 0) ; Y - Change from 0-> 1


This one is little bit different from other gates (which we have reviewed till now).
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XOR gate:
  1. Input Pin A to Output Pin Y for Rising Edge
  2. Input Pin A to Output Pin Y for Falling Edge
  3. Input Pin B to Output Pin Y for Rising Edge
  4. Input Pin B to Output Pin Y for Falling Edge


XNOR Gate:


Above is the "Truth Table" of XNOR gate (for Input Pin A and B, Output Pin Y).

From here, you can see that:

A = 0 , B (0-> 1) ; Y - Changes from 1-> 0
A = 1 , B (0-> 1) ; Y - Changes from 0-> 1

Similarly, for A pin:

B = 0 , A (0-> 1) ; Y - Changes from 1-> 0
B = 1 , A (0-> 1) ; Y - Changes from 0-> 1



In the same way we can also summarize the falling edge:

A = 0 , B (1-> 0) ; Y - Change from 0-> 1
A = 1 , B (1-> 0) ; Y - Change from 1-> 0
B = 0 , A (1-> 0) ; Y - Change from 0-> 1
B = 1 , A (1-> 0) ; Y - Change from 1-> 0


Explanation is same as in case of XOR gate. (copy paste the same paragraph here :) )
You can see that change in the output can't be decided just by seeing/observing one input pin. For B changes from '0' to '1', output can change from '1' to '0' or '0' to '1' depends on the value at A. In other way, I can say that change in the output don't have any pre-defined pattern with respect to Pin B or Pin A indivisibly. It depends on collective behavior of A and B.
Such type of Timing Arcs neither fall in the category of positive_unate nor in negative_unate. These Timing Arcs are Non_Unate.

Timing arc between A-Y and B-Y is Non Unate for both "Negative Rising" and "Positive Rising" signal.

Capturing again:
There are 4 Timing arcs in XNOR gate:
  1. Input Pin A to Output Pin Y for Rising Edge
  2. Input Pin A to Output Pin Y for Falling Edge
  3. Input Pin B to Output Pin Y for Rising Edge
  4. Input Pin B to Output Pin Y for Falling Edge


I am sure, by now, you have developed or revise the concept of Unate in Timing Arc. With the help of Truth table, you can easily figure out the Unateness of any Timing arc. Even If you are going to design any circuit or system (which is not in the list of Standard gates), then you can yourself figure out the Unateness property of different Timing arcs in that system.

We will discuss about that in more detail in next few article. Like how these (Timing Arc , Unateness ) represent in Timing Library, how different values are captured in Timing Library and a lot about the Timing Arcs. :)


Interview Questions


I have tried to capture few Interview questions here which can help you big time during your preparation.
  1. What are the different types of Timing Arc ?
  2. What is Unateness of a Timing Arc ?
  3. What do you mean by Positive_unate of a Timing Arc?
  4. What do you mean by Negative_unate of a Timing Arc?
  5. What is the difference between Non-unate Timing arc and Positive Timing Arc ?
  6. How many Timing Arcs are present in case of Buffer?
  7. How many Timing Arcs are present in a 2 input NAND gate?
  8. How to represent Timing Arcs in the Timing Library ?
  9. A timing arc is positive Unate, if we apply rising edge at the input of the Timing arc, corresponding output will change or not ?
  10. How many Timing arc is present for a 3 input XOR gate?
  11. What's the Unateness of different Timing Arc for a 3 input XNOR gate ?

The newly launched product "VLSI Self Mentorship Program" by Edusaksham, can help you in preparing for Interview and written test. This Course is designed by Industry people. To know more click here.

Sunday, December 4, 2016

5 Steps to Crack VLSI Interview


"5 Steps to Crack VLSI Interview"... Sounds Good :) But before I share with you these Steps, you should know how I have figured out these 5 Steps.
I am in touch with several Industry experts (Technical and Non-Technical Managers), Recruiters (HR people), Universities, Colleges, Professors, Training and Placements Officers (TPO) and Last but not least "Students".
In the last couple of years, I had rounds of very intensive discussions with all of these and after that I have come across major challenges faced by the Students (In the hiring process) and challenges faced by Industry people in recruiting the right VLSI candidates. I will discuss those in detail later on but for today it's important to know "How to break the ICE" :)

Step 1: Evaluate Semiconductor Industry.

When I say evaluate Industry, mean to consider several parameters, which can help you to understand: Are you on right path or not ?

Parameter 1: Is this right Industry for you?
First, you should know why you want to enter in this Industry. If it's because of following reasons then you are on the wrong path.
(Read My previous Article for details. 5 Reason VLSI Industry Not For you)
  1. Want "Huge Money in Short Time"
  2. Are "Not passionate about Electronics"
  3. Want to "Sit back and Relax in Long Run"
  4. Want to "Start your Own business with Zero Investment"
  5. Are "Not Interested In Coding and Automation"

Parameter 2: How Much you know about VLSI/Semiconductor Industry?
This is again a very important parameter before we think about the Semiconductor Industry. Most of the time students apply for VLSI jobs even don't know too much profile, requirements and many other things. During my conversations with Industry experts, this comes out to be an important reason, why they show reluctance to hire a fresher. (Read More : Why VLSI Industry Reluctance to Hire Fresher??)
I have following suggestions for students aspiring career in VLSI Industry:
  1. Increase your knowledge base about the VLSI Industry
    • Read Blogs/ Articles/ Magazines
    • Talk to your Seniors / Friends / Relatives to know more about VLSI Industry
    • Attend Seminars / Conferences which are specific to Semiconductor Industry
    • Like, Subscribe, Join different Groups / Community
  2. Put more effort to fill your knowledge gap
    • Read different books and always try to understand the roots of different concepts
    • If possible, attend different Courses/ Training programs / Workshops

Step 2: Evaluate yourself.

This is something which is required big time whenever you do preparation for anything either it's any competitive exams or Interview or Semesters Exams. You can find a lot of material or instruments/tools which can help you to evaluate your preparation for the competitive exams. Similarly, Internal sessional exams helps you to evaluate for the Semester's exams. But we don't have any mechanism for Self evaluation for Interview or Written Test.
After discussion with Students, I have figured out that it's a big time in demand. Every student is looking for following things:
  • Interview Questions: You can find these over Internet but the point is who captured those questions, Industry people or a Candidate (also similar to you)
  • Solutions or Answer of several Questions: Even if there are good number of questions available, what about their solutions or answers. Are these solutions as per Industry expectations?
  • Follow-up questions: Even if you have questions but are they composed as per Interview pattern? Interview pattern is very much different from the normal exam. (Read More: Interview Pattern Vs Written-Test Pattern)
Check one of my book for VLSI Interview Questions: Static Timing Analysis. It's a Kindle edition.
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author)
VLSI INTERVIEW QUESTION: Static Timing analysis : Puneet Mittal (Author) : (In INR)

Now even if someone gives all these details, we will still be in doubt about...
  • What if Interviewer asks something else?
  • What if I am not able to perform well?
  • How can I assure that I am ready for the Interview?
These questions can be solved when you go through a system which can help you in Evaluation/Assessment.
"No one can win all the time. But you have got to learn from all you do - Both Successes and Failures. Always do a Self assessment."

By - Michael Sachs


I recommend you to try a newly launched program "VLSI Self Mentorship Program" by Edusaksham.
Note: In case you need discount voucher or need to know more, drop me an email. We will be happy to help you.
Whole purpose of evaluation should be to categorise different topics in strong Vs weak basket. In the process of Self Evaluation - the most important thing is to know - where we stand right now. What are the weak and strong areas. If someone help us to find this part then we can easily fix rest of the things (More discussion on this in Step 4).

Step 3: Follow a simple and proven study pattern

When I interacted with students and I asked them about their study pattern, like how do you start preparing for VLSI Interview? Students shared that they start with the advance concepts and what do they do if they get stuck somewhere...the response was, we go back and clear (brush up) those concepts. But according to me, this approach is very complex and timing consuming. Check this picture.


If you jump to the Level 4 directly, then there are equal chances to fall back or say it will take time to understand these concepts or may be you have to come back to level 3 to brush up linked concepts and then again you go back to level 4. Still if something is missing on fundamental side, there is equal possibility that you have to go back to level 2 and then level 4. This iteration can be "N" number of times. Basically you do not realize that there is big iteration or time spend in the whole process.

Now, if someone tell you the study pattern with 100% success rate, then will it be good for you. Like during college – we have semester 1 and followed by semester 2 and so on. Every Semester has predefined syllabi by experts so that you learn fast and don’t loose interest.
Similarly, while preparing for any competitive exam or preparing for an Interview – we should follow a Systematic approach as well, in terms of study pattern.
  • Like what to study?
  • Which topic to read first ? Which is the next topic in sequence ?
  • When to Study?
  • What should be the Weightage of a certain topic and so on.
This pattern is very simple and also proven by experts. Check below figure.


This pattern also has some catches. That's the Part of Next Step. :)

Step 4: Focus on Weak area and that's too as per required Weightage in Interview

There are Students who usually follow the simple and proven study pattern. But still they miss few things and get stuck at first level itself, unable to move forward.
Now imagine, you have started preparing for VLSI interview and decided to start from level 1 (In above diagram it's Number System). After a few days, your Semester exams come or some personal issue or something else which forced you to focus there for next few days. Now these few days convert into month and then you realized that you have to restart. Restart means - restart from the Number System :) because that's the simple and proven approach :). Oh My God once again the same thing. If this thing happens 2-3 times, you loose patience and you may jump to a complex approach :) :)

This happens because we don't know how to move forward in the proven approach itself. The Simple process should be
  1. Evaluate yourself for a certain topic
  2. Identify your Weak and Strong areas
  3. Focus on your Weak area only and then move to next topic
  4. Repeat the process from 1 to 3
In this way, you will not spend your time on your strong area and day by day you will strengthen your weak areas only.

When I say different topics, we need to understand that different topics have different weightage in the Interview process or say as per Industry requirements. I mean to say that in Semiconductor Industry, if we give same amount of time to Number System and Sequential Circuits, it's not justified (even though there are equal concepts to study in both topics). We should also need to know what's required and how much it is required. And as per that only we should divide our time in brushing up different concepts.

List of required Topics/ Concepts can be easily made using Google :) but weightage is not readily available to us from anywhere.
The newly launched product "VLSI Self Mentorship Program" by Edusaksham, can help you in that direction also. Do free login and try sample papers to know more.
Step 5: Profile / Resume Building and Developing soft skills

When I am talking about the Profile building, most of the time students miss a lot of important things. Different Industries need a different type of Resume since they have different requirements. Now if you want to enter in a Semiconductor industry but in your profile you will mention Java, .Net and similar topics, it's not going to help you. It's very important to mention right set of skills in your profile.

Apart from this, Semiconductor industry is very demanding and industry people are too busy. They don't want to spend lot of time with your profile to understand you (knowing that there are lot of other candidates with better written profile :) ). Your profile should be structured in such a way that information can be extracted very easily and as per other's requirement.

There are 3 Major sub-steps of screening based on your profile itself.
  1. Screening by HR or Consultancy Firm: This one is highly focused on the keywords in your Profile. These keywords should be very well placed in such a way that it's automatically highlighted.
  2. Screening by Technical Manager or Leader: This screening is very fast if different sections are placed in a proper manner. There is no standard way for this but if you have divided your profile in sections properly, that reflects your presentation skill.
  3. Telephonic Screening: Sometime telephonic screening happen just to understand the profile. It can be 15-20 mins short process or 45-60 mins long process. Your clear thoughts and in sync with the profile is very important thing here. If you explain something which is not mentioned in your profile, then it becomes difficult for an Interviewer to understand your profile. Here, I recommend to build your profile on your own, don't ask or copy someone else profile :)
To know more about Resume building refer article: How to prepare Good Resume
For the Interview process or pattern, recommend you to refer Face to Face Interview Pattern.

I am sure above mentioned 5 steps help everyone. In case of any query, feel free to drop me a mail or comment.

Tuesday, September 13, 2016

Timing Arc


Before Understanding the Timing Arc, you have to consider the design from the "END USER" point of view. "END USER" doesn't mean only person who are using the End Product (Like mobile Phone or Laptop etc), "END USER" can be anyone. It can be a user of any CHIP , or may be user of a particular IP/Macro or may be a user of a Standard Cell Library.

Lets take an example of Standard Cell (assume NAND GATE). Ask yourself ... What all information you require, If you want to use NAND gate in your design ?

You may be interested to know -
  • How much time (may be in the form of Delay) it will take to respond for a particular Input ?
  • For a Particular Input (Rising or falling), What type of Output (output is rising or falling or no change) you will get ?

These questions are about the Normal Standard Cell (NAND Gate). But what about more complex circuit/CELL like Flip-Flop ( There will be more questions because it has more input and outputs in comparison to Normal NAND GATE.)

E.g For D Flip-Flop : There are
  • 2 Input Pin (D and CLK) and
  • 2 output Pin (Q and Q') and
  • 2 asynchronous Pin (RESET and SET).

It means the number of Timing/Delay information are large in this case. Because there are so many input and output pins and their corresponding combinations are also large in number. Apart of this there are so many dependency of output of one pin on other pin that it's not consider as simple as NAND gate. In general, we are not interested what's going on inside the FlipFlop (Like how many NAND gates are there and how they are connected), we are only interested to know
  • How and when we will get the Output after applying a certain input.
  • Is there any constraint and if yes, then what are those and on what pin.

So basically, in every case (normal combinational gate or a complex sequential circuit) "END USER" has only concern about the relationship between different Pins/Port of a Product (like GATE, FLIP-FLOP, IP).
Note: They may have other concern also, but right now we are talking about Concerns only related to Timing. :)

To answer these questions, we do a lot of experiment (Technical Terminology : Characterization or say Simulation) and come up with a relationship between different Pins in terms of Timing numbers (which is more commonly known as Timing arcs).

Timing Arc represent the timing relationship between 2 Pins of any element or Block or any boundaries. Basically it represent the timing characteristic of the element or block or Boundaries.

Timing arc has a Start-point and an Endpoint.
  • The start-point can be an Input, output or inout.
  • The End is always an output pin or an inout pin (with few exception).
    • Most of the Time arc Endpoint is always an output pin. But there are few cases where it can be input pin.
    • These are constraint timing arc. Like Setup, Hold, Recovery or Removal constraint. These are between input to input pins

On the basis of above understanding, I can say that Timing Arc can be
  • Delay Arc
  • Constraint Arc

Lets consider the Below System, where there are 4 input X1- X4 and 1 output Y1. You can see that there are 4 Arcs between Input pins and output pin. For better understanding we named these as "Input to output Timing Arcs".


Now this is just a small block and End user don't want to know anything about this (what's inside this), if we provide the information about these Input-to-output Timing Arcs. But if we will see what's inside, then it may have Nets and Gates or Cells.


From above figure, you can easily realized that Timing arc can be for NETS also. Now, I can say very easily that Timing arcs can be divided into

  • Net Arc
  • Cell Arc
    • Combinational Cells
    • Sequential Cells

Note: Macro / Custom Blocks also designed using the cells and Nets. So these custom Blocks are again similar to the system/blocks as shown in above figures. Only difference will be that it’s small in size.


In the Next Article, we will discuss how Timing Arc will help you to Answer your questions. We will also discuss more about the Cell Arc and Net Arc. We will also try to capture, how these information is captured in Timing Library.



Wednesday, June 1, 2016

"Fresher" become "Physical Designer" using 3Ps (Passion, Patience, Preparation)


The Journey from Fresher to Physical designer is not that easy as everyone thinking. It need 3Ps, which I always suggest to students/candidates. These 3Ps are:
  1. Passion,
  2. Patience,
  3. Preparation

Last time I have shared a Journey of Sanjay Goyal "From Mtech to Internship" which were around 6 rules:
  1. Complete your required Education with good CGPA/%
  2. Strong Fundamentals and concepts
  3. Prepare good Resume
  4. Understand the Job requirement and prepare your self for the Interview
  5. Keep confidence on your self
  6. Keep trying

But this Journey helps you to understand the real meaning of Abstract words "Passion, Patience and Preparation". One fine Day, "Rinu Johnson" pinged me and shared her success story with me. You can't believe my feeling when I come to know that I (My Articles and Videos) also played a role in her success. After my request - she composed her Journey (which was full of challenges) to share with everyone, so that It can Motivate others.

Here is her ("Rinu Johnson") brief Journey. (I have just convert few words into Links, little bit formatting as easy readability and added line Break at few places. Nothing else is changed).

I have listed my education and my story of entering in to VLSI Industry.

Education:
  • BE in Electronics & Communication Engg from Avinashilingam University, Coimbatore , 2009. , 74%
  • Masters In VLSI Design from Anna University of Technology, Coimbatore, June 2011. 8.75 CGPA
  • Worked as Assistant Professor in the Department of ECE in Sri Eshwar College of Engineering, Coimbatore from June 2011 to Dec 2013.
I was always passionate about to join the VLSI Industry, but due to some personal reasons I was unable to move to Bangalore in search for the same. It was after my marriage I moved to Bangalore and I thought that it was the right time for me look for opportunities in VLSI.

Put forward this idea to friends and relatives but all gave me negative feedback telling that switching from academics to corporate was difficult specially VLSI Industry. But I decided to give a try because later point in my life I shouldn’t regret that I never made a try.

I started browsing about the VLSI institutes and finally ended up with one with was affordable fee ("Indian Institute of VLSI Design & Training" - Bangalore - Now the name is changed to "Industrial Training & Research Institute"). I took the a PG Diploma In VLSI which include both frontend, backend and layout part (February, 2013 – August, 2013).
Frankly speaking, I was not fully aware about the PD Domain and I thought VLSI Industry was fully around the Verilog and system Verilog (design and verification). It was through the course I knew about the Physical Design Domain and I was interested in the same.

After my course I was looking out for job in any of the domain in VLSI. It was tough to get interview calls since I was not a fresher and had a previous academics experience. During my six months of job search I got around 4 interviews. Written test was the worst part I had to again brush up my aptitude etc. I cracked two interviews one in layout and one in PD but due to some project cancellation I was not offered that Job. It was during the job search I stared to have more interest in PD domain.
I then understood that to crack the interview one has to be very strong in basics and should have more understanding in depth about the subject. The six months of job search was created a gap in my career. It was at that time the trainer who trained me in my institute has left and they were in need of a person to take classes for the Physical design. I decided to take up this job and to study more about the Physical design and simultaneously search for Job. It was through the teaching that I gained more deep understanding about the PD domain.

It was at this time I came through the VLSI expert website and got many udemy videos about VLSI. “The more you teach the more you learn” This was true for me . The doubts asked by my students in the institute made me go very deep about the subject and VLSI expert was like reference for me and I recommend the students the same.

After my six months of teaching one fine day through LinkedIn I got an interview call for consultant position in Cadence Design Systems, Inc. I attended the interview and I cracked it easily.

Apart from this, I would like to share few things to the fresher’s who are looking forward to work in VLSI industry.
  1. The fresher’s who are looking for opportunities have to be prepared always because we will not know when opportunity knocks and lot of patience is needed.
  2. Select the domain which you want to work and prepare accordingly.
  3. Deep understanding of the concepts is needed.
  4. It may take some time to get a Job but it’s worth waiting.

I would like to appreciate the work you are doing Puneet (It's Me :) ) because it helps many students. Many college graduates are not aware about the VLSI Industry itself and many colleges also don’t guide the students properly. Its only IITs ,NITs and Tier I college students have better idea about the VLSI industry .
In my M.E batch only I have ended up here remaining all have ended up with teaching because all they knew was after M.E its teaching and nothing else. Some even having interest in core industry end up going for software jobs because they think that only software jobs are lucrative. Keep doing your work and you can reach out to me for any help for the same.


First of all - very thanks to "Rinu Johnson" who took time to appreciate us and share her story so that others don't loose hope and try to understand the real meaning of 3Ps. I am sure It will help other in building their career.

Recommended Article (by VLSI Expert): 5 Reasons VLSI Industry Not for You


I don't think, I have to say anything after her Message to Fresher. Even I have the same opinion.

In case, you want to talk to her (For the Validity of this Testimonial :) ) , you can contact her -
Mail Id: (will share after her confirmation)
LinkedIn Profile https://www.linkedin.com/in/rinu-johnson-86912939

Rinu - Once again - Thanks a lot and Best Of Luck.

Wednesday, April 20, 2016

Journey from M.tech to Internship (Sanjay Goyal)


People always ask me how to get into VLSI Industry and every time, I try to help them with few basic rules.
  1. Complete your required Education with good CGPA/%
  2. Strong Fundamentals and concepts
  3. Prepare good Resume
  4. Understand the Job requirement and prepare your self for the Interview
  5. Keep confidence on your self
  6. Keep trying

If anyone is following above 6 rules, One day they will get their Dream job Or at least the first Success toward the Dream.

Same is the Story of Sanjay Goyal. One day he pinged me and shared his success story with me. I feel proud after hearing the appreciation from his mouth about my Articles and Videos. I asked him to write a short paragraph. I am sure It will help everyone.

Sanjay Scored:
  • 66.9% In Btech.
  • 8.7 CGPA in Mtech.

Here is his short paragraph. (I have just convert few words into Links and added line Break at few places. Nothing else is changed).

"My name is Sanjay Goyal. I completed my M.Tech in VLSI Technology from Sharda University, Greater Noida in 2014.

From the starting of my M.Tech, I had a mindset to get a job in VLSI domain. But the biggest issue was that I had no idea “From Where to Start”.

I joined one institute to learn Verilog as it was subject of my First Semester. Now I started preparing myself for VLSI field. I learnt Linux fundamentals, Basic Analog (MOS, CMOS, OP-AMP etc) and Digital Electronics (Logic Gates, Combo and Sequential Circuits, Memory, etc) along with Verilog HDL.

I used to do lot of web search regarding VLSI topics. Different VLSI-expert's Articles , Several VLSI-Expert's Videos and Different Course of VLSI-academy helped me very much to understand the complete Physical Design Flow. The content is very well categorized, organized and explained with real time examples. It starts from basic level and gradually takes you to advance level.

The second challenge I faced was during my job search. My resume was not getting shortlisted as it was not fulfilling the employer’s requirement. An article How To Prepare Good Resume by Mr. Puneet Mittal on vlsi-expert helped me to prepare a very nice resume which contains all the keywords to match the employer’s requirement. And then I was shortlisted for Mentor Graphics, Truechip Solution and Cadence Design System.

I would like to give sincere thanks to Puneet Sir and whole team of vlsi-expert.com from bottom of my heart. vlsi-expert.com has played a very important role to build my career in vlsi domain as well as to get my dream job inside Cadence Design System. Thanks for your kind support and guidance. Best of luck…… “

First of all - very thanks to Sanjay Goyal who took time to appreciate us. I am sure It will help other in building their career.

Recommended Article (by VLSI Expert): Face To Face Interview Pattern


Now you can see in above Paragraph - There are few important things - which he pointed out.
  • Mindset to get a job in VLSI domain: It was his dream and he was passionate for that. When Dream and passion matches then only you need proper guidance, rest you can do yourself.
  • Learnt Fundamentals: I have mentioned several time that it's always required.
  • Lot of web search regarding VLSI topics: This is something is very important. Now a days, everyone has Internet and free access of Google, Students should use them to understand different Topics. If you explore, you will get all the information. Lot of People are doing a lot of things for the Society. Just you have to use that.
  • Resume was not getting shortlisted: One of the Challenge in getting job is Proper Resume. Sometime people have good technical skills but lack of Soft skills but now a days it's also Important. So you have to focus on that part also.
  • Shortlisted in good Companies: It's not like Companies are not looking for candidates, it's like they need Skill person. Sanjay was prepared with all the basics and fulfilling all perquisite, so he was able to crack all the steps of interview.

I think I have pointed a lot with the help of his Story. In case, you want to talk to him (For the Validity of this Testimonial :) ) , you can contact him -
Mail Id: sanjay.goyal61@gmail.com
LinkedIn Profile https://in.linkedin.com/in/sanjay-goyal-a7352619


Sanjay - Once again - Thanks a lot and Best Of Luck.

Sunday, March 13, 2016

Types Of Clock Skew



Classification Of Clock Skew


In the previous Article, we have discussed about the Skew and the Source of Skew. In this article we will talk about Different Type of Skews.

Classification Of Skew:

There are different ways we can classify Skew. For me, it's very difficult to divide those into different bucket and come up with a tree like structure. But still I am making an effort.

Internal (Intrinsic) And External (Extrinsic)
  • Internal Skew:
    • It is governed by the Devices or Gates.
    • Difference (in time) introduced because of mismatch of propagation delay and transition delay of 2 identical devices or gates.
  • External Skew:
    • This is the difference introduced because of unbalanced Net length or output loading or any other effect (like delay added because of cross coupling).

Process Skew:
As we know, it's not possible to fabricate 2 gates identical in nature. Even though if you take care, there will be some difference in fabrication. This difference can contribute into the propagation delay of the gate under same external environment conditions.
So if we keep all the external factors (parameters) constant/identical, The difference between the propagation delay of 2 identical gates at the output pin, at identical transition is known as Process Skew .(i.e., compares tpd(LH) versus tpd(LH) or tpd(HL) versus tpd(HL) for any two outputs).

For example, if the propagation delay of the fastest output (tpd(LHn)) is 2 ns and that of the slowest output (tpdLH1) is 2.165 ns, then the output skew is: tpd(LHn) - tpd(LH1) = -165ps.
  • Part-to-Part Skew: If these 2 gates are in different devices then these are known as Part-to-Part Skew. This is also known as Package Skew.
  • Output Skew: If these 2 gates are part of same device then are termed as Output Skew. Also Known as Pin-To-Pin Skew.

Pulse Skew:
Pulse skew (tsk(p)) is the magnitude of the time difference between the high-to-low (tPHL) and the low-to-high (tPLH) propagation delays. Pulse skew is sometimes referred to as Duty Cycle Skew.

tsk(p) = | tPHL − tPLH |.

As such the Time Period will be same but the Duty Cycle changes because of Pulse Skew. It plays a very important role when in the circuit we are going to use both Negative and Positive edge of the Clock for Flip flop triggering.

In the Below Figure we have used a Clock Buffer, A represent the Input side and B represent the Output side.

Pulse Skew

Positive and Negative Skew:
Skew can be positive or negative on how the reference clock is chosen. Means if you do A-B > 0 then obviously B-A < 0. So if A is reference, Skew is Positive and if B is reference Skew is negative.

Remember - While calculating the Skew - we do Capture clock delay - Launch Clock delay. So from above sentence don't be confused that it's just a matter of "How you subtract". :) Below 2 figures explain how Positive Skew can be converted into Negative Skew.

Positive clock Skew

Note: This is the Normal circuit we have studied till now. All the skew in this Circuit (above) are Positive.

Negative clock Skew

Note: This circuit is same as the previous one, only difference is the direction of the Clock Vs Direction of the Data flow.

Above figure can help you to understand the basic difference between the Negative and Positive Skew. Now Question come - why we will do this. We will discuss later on in detail that Negative Skew helps in fixing Hold Violation. But there are several other cases where we will not intentionally reverse the direction of Clock but because of Clock distribution Network, it can happen automatically. Below 2 figures are self explanatory. :)

Negative clock Skew

Here you can see very clearly that Clock is entering from the Middle. Right hand side's Flip flops have Positive skew and left hand Side's Flip flop has Negative skew. No one did this intentionally but it just happened because of CTS (Clock tree synthesis) and small negligence from the designer. :)

Negative clock Skew

In the above figure it's clear that Clock tree was good but just because of 2 branches are communicating with each other (which is very normal), Negative Skew scenario developed between FF7 and FF8.

Inter Clock Skew:
When the clocks are in different domains, this is known as Interclock skew. Interclock Skew exists between two registers with different clocks.

Intra clock Skew:
When the clocks domain is same, skew is known as Intra Clock Skew.

Inter and Intra Clock Skew

In the above figure,
Skew between FF1 and FF2 is Intra Clock Skew.
Skew between FF3 and FF4 is Intra Clock Skew.
Skew between FF2 and FF3 is Inter Clock Skew.

I am sure I am not suppose to explain this. :)

In the next article, we will discuss about the effect of the Clock Skew in our Timing Analysis. We will also discuss Different Methods to reduce the Clock Skew between Capture and Launch Flip flop.





Saturday, February 27, 2016

Parasitic Extraction: Introduction


What do you mean by Parasitic Extraction ?

Basically it's a link between 2 domains: Physical Domain and Electrical Domain. Or you can say that it's uses the Physical Information (like Shapes of the design) and provide the Electrical information (Connectivity , Resistance, Capacitance and Inductance).
Everyone of us know very well that Timing is critical for the design and it has dependency on the delay of the network. For calculating the Delay, we should be aware about the Resistance/Capacitance of the Network/Devices. So question is how can we extract this info (R/C) from a layout (which user design/draw) and I can say this very confidently that "Parasitic Extraction do this job efficiently".

So, basically Parasitic Extraction provide the information about the Parasitic Devices which is not included as a part of original circuit design. But these Parasitic Devices effects the Circuit performance in several ways. There are chances that because of these Devices, your circuit stop working or not meet Design Specification. Few examples are:

Effect of Parasitic Devices on Circuit Design:
  • Extra Power Consumption
    • Violate the Power specification
    • Extra power dissipation can increase local Temperature which can effect other parameters
  • Effect the Delay of circuit
    • which can cause of Timing Violation
    • Can impact IR Drop
  • Reduce the Noise Margin
    • which can cause Logic Failure
  • Increase Signal Noise which can
    • Also Change the Logic of the signal (0 to 1) or (1 to 0) - Means Logic Failure
    • Introduce extra/unwanted delay which can impact the Timing numbers
    • Speed up the signal which again impact the Timing Numbers
  • Increase IR drop on power Supply lines that affects Delay


Before we understand other details of this, it's important to know where all we can use it (Parasitic Extraction):
  • During Static Timing analysis:
    • Parasitic Extraction help us to find out the R/C(Delay) of the Network.
    • Delay Help us to do Timing Analysis.
  • During Noise Analysis, Crosstalk Analysis, Signal Integrity Check :
    • For Noise and Cross Talk analysis, it's important to know the relationship between 2 wires. How these wires transfer the information between themselves.
    • Coupling Capacitance is the mode of interaction between them. Parasitic Extraction help us to find the Coupling Capacitance between 2 wires, which help us further to do SI (Noise/Cross talk) Analysis.
  • In Logic Simulation:
    • For Logic Simulation, we need to know Delay information + Connectivity Information.
    • Parasitic Extraction provide the Netlist which has information how different Nets and devices are connected with each other. It help us to do Logic Simulation.
  • During IR Analysis:
    • For IR analysis, Resistance is one of the Important parameter.
    • Parasitic Extraction outputs "Resistance of the Network" which help in IR Analysis
  • Substrate Noise Analysis :
    • In the analog design, a lot of Noise through the Substrate passes to other part of the design.
    • We know that any channel through which any information can transfer have finite resistance. Parasitic Extraction also help to find the Resistance of the Substrate, which help further into the Substrate Noise analysis.

Below 180nm, these parameters (Interconnect Delay and Coupling Capacitance) plays a majority of role, so it's very important to extract this information correctly. But as we all know- Accuracy always hit performance (runtime). More accurate results means more runtime. So there are several ways or say mode in every Parasitic Extraction tool provided by different Vendors so that user can extract only required information. Few of them are:
  • Extract Resistance Only
  • Extract Capacitance Only
  • Extract Resistance and Capacitance both

Capacitance also are of 2 types (or say "Mode") :
  • Decoupled Capacitance
  • Coupled Capacitance

So, you can use any combination to Decrease or Increase the Runtime. It depends on what you want and at which stage.
You may be thinking that what are these Coupled and Decoupled Capacitance. Please refer Article "Coupled and Decoupled Capacitance Extraction Mode".

Runtime of the Extraction can also be decreased by compromising with the Accuracy of the Results. As we all studied in our college days that there are 2 type of network
  1. Lumped Network
  2. Distributed Network
Distributed Network is consider more accurate compare to Lumped Network. So same things apply here also. As much as our Network is distributed, there are chances of more accurate results. As much accurate our results - we will get accurate timing information. So in short it's important to model the Circuit as accurate as much possible. but accuracy impact the Runtime also. So Extracted Tool provide us to control the level of distribution. For example - 1 wire of 10nm can be divided into 10segment or 20segment or may be just 1 segment. Each segment will have their R and C component. using this technique, we can control the Runtime and Accuracy of our output Netlist.

Apart of Above extraction mode, Runtime of each Extracted Tool also depends on several parameters
  1. Design Size
  2. Process or Technology Node
  3. Output format
  4. System Configuration (Or say available Machine Resource) like No of CPU, Memory, Machine Type.

These parameter are mostly out of control from the designer side. Designer can play little bit but can't change a lot. Like If my design is on 45nm and have complex routing, Designer can't change it. EDA tool should be good enough to handle it. And that's the reason- Every EDA group work day-and-night to meet customer requirement.

We will discuss more about Parasitic Extraction, Parasitic Devices and other details more in this series of Articles.

Coupled and Decoupled Capacitance Extraction Mode


During the Parasitic extraction we have a lot of modes to decrease the runtime and extract the desired information. For Capacitance extraction we have 2 sub_modes.
  • Coupled mode
  • Decoupled Mode

If any signal is passing through a wire, it can effect near by wire too. We all know that this is because of charge difference between 2 wire, which help these 2 wire to form a Capacitance.
More clearly if you want to understand - Lets assume there is a Net A and Net B. These two nets are near by. We put a voltage spike on Net A, Net B will get a charge Injection due to the voltage changing on Net A.
Now this Process effect the Signal Flowing through Net A as well as on Net B. In case of Net A, it's consider a Loading effect (Because main signal is flowing through A). In case of Net B, it's consider a noise or Cross talk effect because main signal was flowing though Net A but it effect the signal flowing through Net B.

Coupling and Decoupling mode are related to this particular Cap (Cap between Net A and NetB)

Coupled Mode:
Net-to-net parasitic capacitances are extracted and be part of output Netlist separately. Basically it replicate the Practical scenario and helps in SI (Signal Integrity) analysis.

Coupled Capacitance Extraction

E.g:
C1 NetA NetB 2fF.

Decoupled Mode:
Net to net Capacitance are lumped to ground. I am not saying that this cap will not be extracted but I am saying that this Cap is not going to be part of output netlist as a separate Cap value. This Cap will be the Part of Total Cap (Cap with respect to Ground). So in place of 1 Cap value between Net A and Net B, we will get 2 Cap value.

Decoupled Capacitance Extraction

E.g :
C1 NetA GND 1.1fF
C2 NetB GND 0.9fF.

Capacitive coupling effects are not there in this mode. So You can't use such netlist during the SI analysis. It's comparatively less accurate but it can speed up simulation time a lot.

Just trying to explain the same with one more example.
There are 3 Net. "NetA, NetB, NetC". Different Capacitances are:

NetA -> NetB : 3fF
NetA -> NetC : 3fF
NetA -> GND : 8fF
NetB -> GND : 8fF
NetC -> GND : 8fF

Here NetB and NetC are far away, so not added the Coupling between them. All Nets are of Same Type, so you can see the Same CAP value.

When you extract the Capacitance in the Coupled Mode, Following is the Netlist.

C1 NetA NetB 3fF
C2 NetA NetC 3fF
C3 NetA GND 8fF
C4 NetB GND 8fF
C5 NetC GND 8fF

When you extract the Capacitance in the De-Coupled Mode, Following is the Netlist.

C1 NetA GND 11fF
C2 NetB GND 9.5fF
C3 NetC GND 9.5fF

What happen? Are you not able to figure out ?

CAP between NetA and NetB divided into 2 (here I am doing with equal part but it depends on Wire property and distance with Ground and all) 1.5fF each. Now this 1.5fF is added to NetB to Ground and NetC to Ground.
So value become 8 + 1.5fF = 11.5fF For Both NetB and NetC.

For Net A , it become 8 + 1.5fF (from NetB) + 1.5fF (from NetC) = 11fF.

Monday, February 8, 2016

Setup and Hold Violation: Advance STA (Static Timing Analysis )



Why, Setup Depends On Max Data path Delay and Hold Depends on Min Data Path Delay ?


Let me start with the important points those were the outcome of previous Article...
  1. Setup and Hold Check is associated with the Capture Flip Flop and Capture Clock Edge.
  2. Setup and Hold Time Create a window across the Capture Flip Flop and for proper operation of Flip flop, Data should be stable during that window.
  3. Data launched by "Launch FF" (FF1) at clock edge "1" is going to capture by "Capture FF" (FF2) at clock edge "2" (Means Next clock Edge).
  4. If data reach D2 pin of FF2 with in Setup time window of Next Clock Edge, That is consider a Setup Time Violation. In below figure, if the time when B reaches D2 lies in Gray area across edge "3" (or the time when A reaches D2 lies in Gray area across edge "2"), it's a Setup Violation for Timing path "Path1".
  5. If data reach D2 pin of FF2 with in the Hold time window of Same Clock Edge, That is consider a Hold Time Violation. In the below figure, if the time when B reaches D2 lies in Red Brown area across edge "2", it's a hold Violation for Timing path "Path1".
  6. Remember - If "B" reaches Red brown area across edge "2", it will unstable Data "A" And as per the Hold requirement - A should be stable in the Red brown area across edge "2".
  7. From the above 3 points (#4,#5,#6), it's clear that Data "B" has a window between Two clock edge ("2" and "3") in which if it reach D2 pin of FF2, there will be no Setup and Hold Violation. And this is our requirement.

Setup and Hold Time across Capture Clock Edge

Now, you can easily say that data "B" will take a certain time to reach from Q1 to D2, you will calculate that part and you can easily figure out whether "B" is in Gray area (across "3") or Red Brown Area (across "2"). Once you know this information, it's very easy to fix setup and hold Violation. Then Why do People always so much worry about this ? Why, Fixing Setup and Hold Violation is so complex?

Whatever you are saying is 100% correct but you have added a certainty in above approach ("B" will take a certain time to reach from Q1 to D2). This certainty has a lot of hidden conditions.

You can understand this in the way - if someone ask you - How much time you will take to reach from location "X" to Location "Y" ? And you have to give specific numbers. I am sure you will answer something like this (I took some random numbers for clear understanding).
  • It will take 60min to reach if I am driving a Car with a constant speed of 50miles/Hr and No Traffic Signal Stops me.
  • It will take 65min to reach if I get all the Traffic Signal RED.
  • It can be faster( near about 45min), if I ask My driver to drive my Car.
  • In case of Peak Hr, there will be a lot of Traffic on road and during that time, It will take approx. 90min. And it doesn't matter whoever drive

I am sure you got my point. :) Now from Data point of view, If I will ask you same question once again "How much time Data "B" will take to reach D2 pin from Q1 pin ?" :) :)
Now, your answer will be some thing like this (if not - means you didn't get my point in above example :) :) ).
  • It depends on previous data and current data. Means whether Data switches from 0->1, 0->0, 1->0 or 1->1.
  • It depends on What type of Cell are we using ?
  • It depends What's the environment condition? Is there anything which can change the Delay of the Path ?
  • It depends if Path is fabricated as per your specification (no manufacturing defects).
  • It depends on which PVT conditions we are calculating the delay?

So basically, you will come up with a lot of conditions and you will ask back a lot of questions before calculating and providing a specific value. There may be few questions which I can answer with definite numbers but lot of answer will be in a range. Like (my answer may be something like this)
  • Environment temperature can vary between -40deg to 120deg.
  • There will be only 2 type of transition between the Data in this path (0->1 and 1->0).
  • We will use only LVT cells but that can be of any driving strength.
  • I can't give you the guarantee that there will be no Manufacturing Defects, but yes foundry provided a "range" of data to model those defects.
  • We have figured out 10 PVT corners for which this timing path should work without any violation.

So what's does it mean -Even, I have all the Answer but every thing is in range. Because I don't know who will be the end use?, in which environment condition this chip is going to use (Timing path belongs to whatever chip)?, What will be the condition of chip after 2 year?, During the manufacturing whether it will be in the middle of the wafer or at the edges? I myself have a lot of uncertainty in my answer.
As inputs are in range - you will calculate the delay (Time take by "B" to reach Q1 to D2) using all the combination and I can bet that you answer will be in a range not a certain value. :) :)

By now, you should be clear - why in real world we don't talk about the specific numbers. :):)

So it means "B" has a min and max time to reach D2 pin.
Min value means - as per the different combination of Input, "B" will not reach D2 pin before this minimum value.
Max value means - as per the different combination of Input, "B" will not reach D2 pin after this maximum value.

So now lets revisit the Setup and Hold Check definition and requirement (along with the Diagram).

Setup and Hold Violation Condition as per min and max data value

In the above figure, Data "B" is divided into a range (from Bmin to Bmax). Now, you can easily visualize the condition of Setup and Hold Violation.

Setup Violation:
  • If "Bmax" lies in the Gray area across Edge "3", it's consider a Setup Violation. OR
  • I can say that if Data Range (Red area across data "B") overlap Gray area across Edge "3", it's a Setup Violation.
  • It means for Setup Check, we consider "Maximum Data Path Delay" (In above example, it's "Bmax").

Hold Violation:
  • If "Bmin" lies in the Red Brown area across Edge "2", it's consider a Hold Violation. OR
  • I can say that if Data Range (Red area across data "B") overlap Red Brown area across Edge "2", it's a Hold Violation.
  • It means for Hold Check, we consider "Minimum Data Path Delay" (In above example, it's "Bmin").

Now 1 interesting question - Is it possible that Bmin and Bmax will overlap Gray (across Clock Edge "3") and Red_Brown (across Clock Edge "2") area at the same time ? Yes It is... And if this Possible - what does it mean ???
Same path has Setup and Hold violation at the Same Time.

Setup and Hold Violation at the same time in the same timing path

I think, I am able to successfully answer both questions which you have asked me in the end of Previous Article.

So for Doing the Setup and hold checks, you have to give a lot of inputs to the Timing Analysis tool and then it will do the calculation, figure out the min and max delay of the Data path and check whether there is any overlap or not with the Setup and Hold Window across The Clock Edge. If we miss any input, report provided by the Timing analysis tool will not be correct. That's the reason we do the Timing analysis several time during the whole design Cycle. As we move forward, we get more clarity about the inputs/condition, we feed those inputs to timing analysis tool and try to fix setup and hold violation incrementally.
Other flip side of this - It's not a easy job and Run time will be huge.

So the Question come - How can we reduce the complexity of the Inputs and also decrease the Analysis time. For this, different Timing tools have different methodology but a very common way is "Adding the Pessimism in the calculation of Delay Value". This helps even in providing less input (or say impose less conditions) to timing tool and it become fast.

I am not suppose to mention that:
After the Pessimism, Min value of Data path Delay < actual min_value of Data path Delay.
After the Pessimism, Max value of Data path Delay > actual max_value of Data path Delay.


If you are able to fix Setup and Hold Violation in this condition - means It's already ready for actual value. But problem comes when you are not able to fix with these Pessimistic values. Then we have to debug a lot (or say dig a lot) and has to figure out
  • Whether these are real violations or not?
  • If These are real violation, what's the root cause of that and what's the solution of that?

We will discuss in detail about these questions in next Article.






Sunday, February 7, 2016

Setup and Hold Check: Advance STA (Static Timing Analysis )



Setup and Hold Check


In this series of articles, I will discuss Advance topics related to Setup and Hold Violation. I will try to explain following things
  • How does Timing Tool calculate/report Setup and Hold Violation ?
  • What are the different Reasons for Setup/Hold Violation reported by Timing Tool? Those are Real violation or limitation of tool?
  • Timing Tool take pessimism approach for calculating Setup/Hold violation, How to debug that part before reaching to conclusion that these are real or false Setup/Hold Violation.
  • If there are several Setup/Hold violation, How to narrow down and find out the real cause of the Issue.?
  • What are different methods to fix these violations ?
  • Which approach/Method we should use in which case?

There are list of other questions/confusions, which I will try to cover in this series.
Now, lets start With the same Question "What is setup and Hold Violation?" :)

Basic Circuit of Capture and Launch FlipFlop

Above diagram is very basic Diagram which we always use in STA. In the above diagram,
  • There are 2 Flip flops - FF1 (Launch FF) and FF2 (Capture FF). These Capture and Launch are with respect to Timing path (Path1).
  • 2 Clocks : CLK1 and CLK2 - I assume the ideal one (Means No Skew) for simplicity purpose.
  • There is a small delay between CLK_S (source Clock) and CLK1/CLK2 because of Buffer (Buf2).
  • Every Clock edge is marked with number, so that I can easily refer those number in place of saying "first edge or second edge".
  • Net delay, we are considering Ideal right now.

We know very well that the data launched at Clock Edge "1" by the Launch Flip flop (FF1) is going to capture at Clock edge "2" by the Capture Flip Flop (FF2).
Note: If you don't able to understand this concept, please read the Static Timing Analysis Series.

Setup and Hold Checks are related to Capture Flip Flop. It means we have to understand These concept from the Clock edge at the Capture Flip Flop.
In the below figure,
I took the 2nd Edge of the CLK2 (CLK2 is the capture Clock for Capture FF2), it will help us to understand more clearly.
Data launched by CLK1 (which is associated with Launch FF) at edge "1" is "A" and at edge "2" is "B", which reach at "D2" as per the diagram.
Setup Time and Hold Time of FF2 is marked by Gray and Brown box across the CLK2.

Setup and Hold Time

As per the Setup requirement of FF2 - Data "A" should be stable at "D2", "Setup time" before the "2" clock edge of CLK2.

As per the Hold Requirement of FF2 - Data "A" should be Stable at "D2", "Hold Time" After the "2" Clock Edge of CLK2.
  • There is only one data which can make "A" unstable after the "2" Edge of CLK2 and that's the "B" (which is launched at "2" Edge of CLK1), if it's reaches at "D2" with in the hold time range.
  • So I can also say that data "B" should reach at "D2" only "Hold Time" After the "2" Clock Edge of CLK2.
  • In the above example, "B" is outside the Brown Box (correspond to Hold time), it means "A" will be stable during that time.

And that's the reason,
During the Setup violation - We talk about:
  1. The Same Data: In above example "A".
  2. Two different Clock edges: In above example - "1" of CLK1 (Launched "A") and "2" of CLK2 (Captured "A").
During the Hold Violation - We talk about:
  1. The Same Data: In above example "B".
  2. Same Clock edge: In above example - "2" of CLK1 and CLK2

If "A" is in the Gray box - It's a Setup Violation.
If "B" is in the Brown Box - It's a Hold Violation.

Theoretically, above things looks good but if we are not providing any input data to the design, how come Timing tool figure out what data is launched by CLK1 at "1" or at "2" ? I think you may have this question. If that's the case, how can Timing tool do the calculation for Setup and Hold Violation. :)
Below diagram can help you to understand that part.

Setup and Hold Violation

In the above figure, "A" is the data launched by CLK1 at "1" and "B" is data launched by CLK1 at "2" and diagram shows the time instant when they have reached at D2. Now we are only talking about the Capture Clock CLK2. We have picked 2 edges "2" and "3" (I can also pick "1" and 2" but these edges will help you to understand the concept easily).

If Data "B" reach early (at D2),there are chances that it may come in the Brown Part (of Edge "2") - Means make "A" unstable - That Means Hold Violation in this path.

If Data "B" reach late (at D2), there are chances that it may come in the Red Part (of edge "3") - Means Not stable before Setup Time - That Means Setup Violation in this path.

During the Timing Analysis -
  • Tool know the frequency of Clock - Means Time period - Means It know the Time difference between the 2 Clock Edges. In above example, if "1" is the reference that tool know very well when "2" and "3" will come.
  • How much Time Data will take to travel from Q1 to D2 - depends on the Delay of the circuit. Which Tool know very well.
  • From The Flip Flop Library, it can easily extract the Setup and Hold time.
  • Whether Flip flop is Negative edge triggered or Positive edge triggered, can easily extracted by Flip Flop Library.
  • Other information, Like Net delay, Clock path Skew depends at what stage you are doing the Static Timing analysis and accordingly tool uses those information.
So, in short Timing Tool have all the information which are necessary to do the Timing checks. It don't need the any signal travel information. Analysis result also not going to change if you give input 101 or 010 or 111 or 000 ..etc.

In general, with the help of Time Period, Clock Skew (if it's there), Setup and Hold Time - Timing Tool come up with a window (min and max value) for the Data path Delay.

If Delay is less then the MIN value of that Range - It's a Hold Violation.

If Delay is greater then the Max value of that Range - It's a Setup Violation.


I am sure you are clear what I have tried to explain you. But now you may have few other questions.
  • Delay of a path should be a single value, then why we talk about the max/min delay of a path, maximum delay of data path for Setup check and minimum delay of data path for Hold delay ?
  • As per above explanation, it's very clear that in your circuit for a timing path either there should be a Setup violation or Hold violation. But How come you have seen/heard setup and hold violation at the same time?
I will explain this part in the next coming Articles in more detail.

Wednesday, January 20, 2016

Skew



Introduction and Source Of Clock Skew


It's very important to understand the Skew and how it impact the timing analysis. Few different flavor of Definition. :)
  • It's a difference between the clock arrival time across the chip.
  • It's the time delta between the actual and expected arrival time of a clock signal.
  • Clock skew is the timing differences between signals in a clock distribution system
  • Variation of arrival of clock at destination points in the clock Network.


As you can see in this pic, positive edge of both the clock signal (CLK1 and CLK2) has some time delay even when there is Same clock source (CLK_S). This Time delay is known as CLOCK SKEW.

There are lot of thinks which I was trying to write down here but later I decide to record that part. Please refer these videos for more detailed Understanding about the Clock Skew.




Source of Clock Skew


In general Clock skew has 2 Distant sources.
  1. Clock Driver or Clock Buffer
  2. Clock Distribution System

Clock Driver and Clock Buffer:
Clock Buffer is a special type of Buffer which is required to keep the Transition with in a certain range. We will discuss this in detail in terms of Layout and all but important thing these are designed specially for Clock path. Ideally all the clock buffer / clock driver, all the internal circuit elements should matched perfectly so that the propagation delays become identical. In a practical clock driver there are many variables which can effect the propagation delay when though paths are equivalent and these effects /parameters contribute to skew. Few of them are:
  • The layout and electrical characteristics of the gate components
    • Output Load Vs Current characteristic
    • Input Transition Vs Delay Characteristic
    • Different Resistance of Internal VIA and Metal wire
  • The location of those components relative to ground and VCC
    • Different Capacitance which can effect Charging and discharging time
    • Internal Coupling Cap difference
  • In Die Process, Voltage, Temperature (PVT) variation
    • Different clock buffers with different channel lengths
    • Local drop in voltage leads to increased buffer delay
    • Device mismatch across die
    • Hot spots lead to increased gate delay

Clock Distribution System:
This is second source of clock skew which is playing a significant role in lower nodes. The Clock buffer is important in clock distribution but how that distribution is done is very important. If it's uneven, then you will notice a skew between 2 Clock. Practically what ever you do, you can't design 2 wires with all environment identical. And because of this difference you will see a difference in Net delay, which contribute in SKEW. Few source of difference are:
  • Wire Coupling
    • Coupling will be different on different clock routes.
    • Near by Signal Lines can distort (add delay) the Clock signal because of coupling effect.
    • Nearby Power Line can also effect the Wire coupling.
  • RC Mismatch
    • Clock routes not all of equal length.
    • Latches or Flip Flop not all equal distance from Clock buffer.
    • Device Loading
  • Process, Voltage, Temperature (PVT) variation
    • Hot spots lead to increased wire delay.
    • Manufacturing Effects can change the width/thickness of wire, which result different delay.
  • Unequal Buffering
    • Unequal buffering can cause additional skew due to rise time/fall time dependent delay in buffers.
    • Change the Load of previous Stage.
    • Contribute in different transition time means different wire delay.

In summary, I can say that if you need to understand the Sources of Skew, you need to understand how many type of delays are there ? How delay changes with respect to different parameters like output load, Input transition, Temperature and all.
You can refer few of my previous articles which can give you some direction to think. I will see later, if there is any need to add more content.

Delay related Articles:

If you want to understand how Variation during the fabrication can change the Metal width / Thickness, which are related to R and C value (Delay), then you can refer below series of Manufacturing Effect.

PS: I hope above articles help you to understand the Source of Skew. Even if you have any question, Drop me message.

Interview Question:

There are lot of questions can be asked on this topic. Few I am listing here. All the Answer are hidden in above material. :)
  1. What do you mean by Clock Skew
  2. Skew is related to specific clock domain or it can be across any Clock domain ?
  3. What are the different reason for Clock skew?
  4. I have instantiate same Clock buffer in each of 2 clock path, is there any possibility of Clock skew even in that case ?
  5. How can variation in Power supply contribute in Skew?
  6. Cell Delay has dependency on Input Transition and Output Load. But if on 2 different clock, Buffers are places at the same distance and output load is also same, whether there is any possibility for Skew even in that case ?

Note: Basically, Most of the question will be related to Delay and how that changes with different parameters.

In Next Article, we will discuss More about Skew Like "Different type of Skew", "Impact of Skew on Timing", "What are different Methods for reducing Skew", "What are different Methodology of Design which can help us to reduce the effect of Skew" and a lot more. Stay tune and enjoy reading.






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