## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Tuesday, September 13, 2016

### Timing Arc

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

Before Understanding the Timing Arc, you have to consider the design from the "END USER" point of view. "END USER" doesn't mean only the person who are using the End Product (Like mobile Phone or Laptop etc), "END USER" can be anyone. It can be a user of any CHIP , or may be user of a particular IP/Macro or may be a user of a Standard Cell Library.

Lets take an example of Standard Cell (assume NAND GATE). Ask yourself ... What all information you require, If you want to use NAND gate in your design ?

You may be interested to know -
• How much time (may be in the form of Delay) it will take to respond for a particular Input ?
• For a Particular Input (Rising or falling), What type of Output (output is rising or falling or no change) will you get ?

These questions are about the Normal Standard Cell (NAND Gate). But what about more complex circuit/CELL like Flip-Flop ( There will be more questions because it has more input and outputs in comparison to Normal NAND GATE.)

E.g For D Flip-Flop : There are
• 2 Input Pin (D and CLK) and
• 2 output Pin (Q and Q') and
• 2 asynchronous Pin (RESET and SET).

It means the number of Timing/Delay information are large in this case. Because there are so many input-output pins and their corresponding combinations are also large in number. Apart of this, there is so much of dependency of output of one pin on other pin that it can not be considered to be as simple as NAND gate. In general, we are not interested what's going on inside the FlipFlop (Like how many NAND gates are there and how they are connected), we are only interested in knowing:-
• How and when will we get the Output after applying a certain input?
• Is there any constraint and if yes, then what are those and on what pin?

So basically, in every case (normal combinational gate or a complex sequential circuit) "END USER" has only concern about the relationship between different Pins/Port of a Product (like GATE, FLIP-FLOP, IP).
Note: They may have other concern also, but right now we are talking about Concerns only related to Timing. :)

To answer these questions, we do a lot of experiments (Technical Terminology : Characterization or say Simulation) and come up with a relationship between different Pins in terms of Timing numbers (which is more commonly known as Timing arcs).

Timing Arc represents the timing relationship between 2 Pins of any element or Block or any boundaries. Basically it represents the timing characteristic of the element or block or Boundaries.

Timing arc has a Start-point and an Endpoint.
• The start-point can be an Input, output or inout.
• The End is always an output pin or an inout pin (with few exception).
• Most of the Time arc Endpoint is always an output pin. But there are few cases where it can be input pin.
• These are constraint timing arc. Like Setup, Hold, Recovery or Removal constraint. These are between input to input pins

On the basis of above understanding, I can say that Timing Arc can be
• Delay Arc
• Constraint Arc

Lets consider the Below System, where there are 4 input X1- X4 and 1 output Y1. You can see that there are 4 Arcs between Input pins and output pin. For better understanding we named these as "Input to output Timing Arcs".

Now this is just a small block, and if we provide the information about these Input-to-output Timing Arcs, End User doesn't want to know anything else about this i.e. what's inside this. But if we will see what's inside, then it may have Nets and Gates or Cells.

From above figure, we can easily realized that Timing arc can be for NETS also. Now, we can say very easily that Timing arcs can be divided into

• Net Arc
• Cell Arc
• Combinational Cells
• Sequential Cells

Note: Macro / Custom Blocks are also designed using the Cells and Nets. So these custom Blocks are again similar to the system/blocks as shown in the above figures. Only difference will be that it is small in size.

In the Next Article, we will discuss:-
• More about the Cell Arc and Net Arc.
• How these informations are captured in Timing Library!

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10. Timing constraints mean in easy understanding way

11. Why arc formed between net and cell,mean why we use this term

1. it is formarion of arc. it is a relationship between 2 pins either with respect to the transistion or output load. it is not always the output is expected somehow we can understand the reason behind it by undersanding the timing arcs.

12. Is it possible that there are many arcs defined between one input pin and one output pin ?