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Thursday, November 15, 2018

TCL Practice Task 2 (Scripting Language)

TCL is very important from automation point of view in VLSI Industry but students are lacking bigtime. Even if they learn, they face problem to understand the uses of TCL in VLSI Industry. In these series of articles, I am listing down few of the small projects or say programs or say exercise which can help anyone to understand the use-model of TCL in Industry. As a fresher, if you try at least once, it will boost your confidence. If you are able to automate below few task, more then 50% of work (based on TCL) can be done easily.
This is second part. If you have missed first part, please visit it. Because to understand this Task, you should have Task 1 program handy. :)

If you have completed previous task (task 1), I am sure now you are good in file handling.

Task 2:- Mapping Two Files

Step 1: Create 2 Input files ("file_input1.txt" and "file_input2.txt")
Content of "file_input1.txt" is same as in the previous Task. So, you can copy file from last program. Snapshot of both the files are present below.

Input File: “file_input1.txt”

    Name        Delay    Trans    Load
    ---------------------------------------------
    AND1_2X      1.50ns    0.1    1.25ff
    AND1_3X      1.75ns    0.2    1.98ff
    AND2_3X      2.37ns    0.3    2.27ff
    AND2_4X      1.82ns    0.5    2.54ff
    NAND1_2X    2.14ns    0.2    1.69ff
    NAND2_3X    2.48ns    0.3    2.11ff

Input File: “file_input2.txt”

    CELL_1:    AND1_2X
    CELL_2:    AND2_3X
    CELL_3:    AND2_4X
    CELL_4:    NAND2_3X

Step 2: Reuse TCL Program of Task 1 and convert into procedure or procedures.

Step 3: Write a TCL program, where you will read both input files "file_input1.txt" & "file_input2.txt" and as per the CELL name present in second file (e.g. AND1_2X ...), you have to extract below data and display it in the below format.

    Name        Trans    Load    Delay    Total_Delay
    ----------------------------------------------------------------------------
    AND1_2X      0.1    1.25ff    1.50ns      1.50ns
    AND2_3X      0.3    2.27ff    2.37ns      3.87ns
    AND2_4X      0.5    2.54ff    1.82ns      5.69ns
    NAND2_3X    0.3    2.11ff    2.48ns      8.17ns

Total Delay = Delay of Cell + Delay of Previous stage
So, in our case,
    Delay of AND1_2X = 1.50ns + 0ns = 1.50ns
    Delay of AND2_3X = 2.37ns + 1.50ns = 3.87ns
    Delay of AND2_4X = 1.82ns + 3.87ns = 5.69ns
    Delay of NAND2_3X = 2.48ns + 5.69ns = 8.17ns

Note:
  • All the above calculations, you have to do with in TCL Program.
  • You have to reuse TCL program of Task 1.
    • Reading of File "file_input1.txt" should be with the help of previous program only.
    • Rearranging the data should be using previous program.
    • Writing data should be as per previous program.

Step 4: Print the above formated data onto the terminal & in output file "file_output2.txt"

Learning after this Program:
  • How to Open & Close 2 Input files simultaneously
  • How to Read or Write from/in a file
  • How to save data in List and do different operation on that
  • How to do Matching or say comparison of Data
  • How to select only a specific data
  • How to do mathematical calculations
  • Different commands use-model
    • list, lindex, lappend
    • Foreach loop, While loop, If-else loop
    • gets and puts
    • split
    • expr
    • incr
  • How to manage single space, multiple space
  • Regular expression concepts
  • Procedure concepts (proc in tcl)
    • How to write a Procedure
    • How to pass a value to Procedure
    • How to call a Procedure
    • How to get return from a Procedure (return command)

Industrial Use of this Task:
Most of the time, we work on automation of data in Industry.This data present in the form of report file (.rpt file) or output file or may be logfile. After reading data, we have to do a lot of operation (mathematically) and has to represent the data as per our requirement.
For example,
  1. Timing Report have a lot of information about several Timing paths. You may have to create a automation to find out only slack of specific paths mentioned in other file.
  2. SPEF file has C (cap) information of Nets. You want to compare 2 SPEF files of same design generated after making certain changes in design. This type of automation create a final report of Delta Cap for all Nets present in either SPEF file. Analysis of this final report (created after automation) may help you to fix design issues.
There are lot of such examples. I will try to list those sometime later. :)

I am sure this article will help you. In the Next article, we will discuss about a task where you have to take inputs from user in runtime (means during the execution of Program).


-By Rajat Bansal
(Btech-EC:- 2019 Passout)
(ABES Engineering College)


-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

Wednesday, November 14, 2018

TCL Practice Task 1 (Scripting Language)

VLSI Industry has requirement of TCL (a scripting language). Lot of Institutes helping students to learn this language. But somehow students don't know much about the use of this in real VLSI World. In this article, I am listing down few of the small projects or say programs or exercise which you should try at least once before entering into the VLSI Industry. If you are able to automate below few task, more then 50% of work (based on TCL) can be done easily.

Task 1:- Input Output File Handling & Rearranging Data

Step 1: Create a file and named it "file_input1.txt" (Content of "file_input1.txt" is given below - Remember, you have create file exactly same as given. All spaces and format should be in same manner)

Input File: “file_input1.txt”

    Name        Delay    Trans    Load
    ---------------------------------------------
    AND1_2X      1.50ns    0.1    1.25ff
    AND1_3X      1.75ns    0.2    1.98ff
    AND2_3X      2.37ns    0.3    2.27ff
    AND2_4X      1.82ns    0.5    2.54ff
    NAND1_2X    2.14ns    0.2    1.69ff
    NAND2_3X    2.48ns    0.3    2.11ff

Step 2: Create a TCL based program which will read input file ("file_input1.txt) and rearrange the data as per below format.

    Name        Trans    Load    Delay
    ---------------------------------------------
    AND1_2X      0.1    1.25ff    1.50ns
    AND1_3X      0.2    1.98ff    1.75ns
    AND2_3X      0.3    2.27ff    2.37ns
    AND2_4X      0.5    2.54ff    1.82ns
    NAND1_2X    0.2    1.69ff    2.14ns
    NAND2_3X    0.3    2.11ff    2.48ns

Step 3: Print the above formated data onto the terminal & in output file "file_output.txt"

Learning after completion of this task:
  • How to Open and Close file
  • How to Read or Write from/in a file
  • How to save data in List and do different operation on that
  • Different commands usemodel
    • list, lindex, lappend
    • Foreach loop, While loop, If-else loop
    • gets and puts
    • split
  • How to manage single space, multiple space
  • If you are using regular expression - then things will be different but as such this program can be written without any regular expression.
  • If you are new to Linus environment then few more learning after this task
    • How to write a file using any unix editor
    • How to source a file and execute a program
  • If you want to use Procedure (equivalent to functions in C)
    • How to write a Procedure
    • How to pass a value to Procedure
    • How to call a Procedure

Industrial Use of this Task:
Most of the time, we work on automation of data in Industry.This data present in the form of report file (.rpt file) or output file or may be logfile. After reading data, we have to rearrange that data as per required format or say template (may be because of any other tool requirement or other scripting requirement or creating graphs/charts etc.)

I am sure, it will help you. In the Next article, we will discuss another Task with multiple file handling and data comparing concepts.

-By Rajat Bansal
(Btech-EC:- 2019 Passout)
(ABES Engineering College)


-Supervised By Puneet Mittal
(Founder & Director)
(VLSI Expert Private Limited)

Tuesday, September 4, 2018

The Job Before the Job – How to Write a Killer Resume

Author Article: (By Lucy Wyndham)

Those looking to get into the world of semiconductor engineering are facing one of the most competitive job markets out there. According to the U.S. Bureau of Labor Statistics, the projected market growth for materials engineers is only 2% between now and 2026. This stat may sound as intimidating as an interviewer’s questions, but don’t worry. This just means you need to prepare for the career as thoroughly as possible, and this starts with writing an irresistible resume.

The Basics
Errors have always been resume-killers. One misspelling here or glaring grammatical gaffe there is oftentimes all it takes for a resume to get tossed in the wastebasket. When you’ve typed up a resume, carefully proofread it and fix all the errors you spot. When you’re done, comb over it again – chances are you missed something. Not doing so could kill your hopes before they even spring forth.
A good-looking resume is more than just making sure there aren’t any mistakes, though. It must be easy to read and possess an agreeable aesthetic flow. Use a legible font that’s sized to allow for a decent amount of white space on the page, as that will make it easier to read. Also, stick to white or cream-colored paper, as it’s very difficult to take a resume on colored paper seriously.
Additionally, don’t fudge. This not only includes your qualifications or your past job info, but also your technical skills and proficiencies. If a job is asking for, say, Excel skills, this means they are going to expect you to work with a spreadsheet. This could be a problem if you don’t know what you’re doing.

Modern Tips
Because of the Internet and the power of social media, it’s not enough to just build your resume with achievements and proficiencies. You need to have an online presence. Studies show a whopping 93% of recruiters will seek out your online profiles before making the call to interview you.
Therefore, be proactive here and put your social media links on your resume. Putting a link to your LinkedIn site, for instance, will make your resume more appealing. After all, nobody will have to poke around the net trying to figure you out.
Following these tips won’t necessarily guarantee a phone call from a potential employer. However, they will increase the likeliness of your resume getting noticed and considered. That may seem like a small step, but considering the competitiveness of the semiconductor engineering job market, it’s an important step to take.

-By Lucy Wyndham
(lucy.writer@lumenmail.net)

Tuesday, May 1, 2018

Digital Electronics - Mux Based Interview Questions


As a fresher or experienced candidate, digital electronics always play an important role in VLSI Interview. Whatever be the profile, it doesn't matter. Lot of candidates call me or message me and ask
  • What type of questions can be asked in Digital electronics ?
  • Which book/s is/are good for preparation?
  • What all topics should be cover ?
and lot more such type of questions.

It's very difficult to answer such questions because Digital electronics is so vast that no one can cover it 100% with in 1 month (max time we get before any interview). So what's the best way to prepare. I am capturing few topics from Digital electronics one by one which looks to me very important. I am also trying to capture questions which can be asked by any Interviewer. If you can focus on these topics or say questions - I am sure - it will give you a good amount of confidence for any Interview.

Note: At the end, I am trying to capture few common mistakes, more than 50% candidates do during interviews. I hope, it will help all of you to get the right answer and understand the expectation of Interviewer.

Multiplexer based Interview Questions:


  1. Describe the operation of Multiplexer
  2. How many select lines are there for 12 : 1 MUX ?
  3. How many input pins are there in a 2:1 MUX ?
  4. How can we convert 4:1 Mux into 2:1 Mux ?
    1. Any other method for converting 4:1MUX to 2:1, where no need to short "Select line" ?
  5. How many 2:1 MUX require to make 16:1 MUX ?
    1. Draw diagram with proper labelling
  6. What's the difference between MUX and Encoder?
  7. Draw internal circuitry of 2:1 MUX using only NMOS, PMOS and CMOS?
  8. How many Transistor (transistor count) in a 2:1 MUX?
  9. Design an AND gate using MUX.
  10. Design a D Flip-flop using MUX.
    1. This is very common question and lot of follow-up questions on the basis of your answer. Below are few ...
    2. Mux'ed based "Positive/Negative Triggered D-Flipflop"
    3. Mux'ed based "Positive/Negative level latch"
    4. Advantage/Disadvantage of using Mux'ed based Flipflop.
  11. What's the advantage/disadvantage using MUX based AND gate over normal CMOS based AND gate?
  12. Do you know anything about Clock gating?
    1. Draw a circuit for clock gating using AND gate
    2. Draw a circuit for clock gating using OR gate
    3. Draw a circuit for clock gating using MUX
    4. Out of above 3 which one you prefer and why?
  13. Questions where Interviewer connect 1 input of 2:1 MUX with the ground and ask you the output function. e.g
    1. If in a 2 : 1 MUX, we connect D0 input with ground, what will be the output?
    2. If we interchange the signal applied at D0 & D1 in above figure, what will be the output?
  14. In Mux'ed based AND gate, if position of Inputs are Interchanged (below fig a and fig b), is there any difference from timing perspective (Delay perspective)? Justify your answer in both case (Yes/NO).

There can be more questions but unfortunately, not able to recall them. Anyone has any other questions - please help me to add here. Else, I will update this list whenever I am able to recall. :)


Common Mistakes in Different Questions:


Common Mistake Related to Question 1:
While explaining the operation of Mux, candidates generally miss "select lines". If Interviewer ask to draw the diagram of MUX, candidates draw diagram without proper labelling. This is the area where anyone can confuse you. See below symbols & try to understand why I have mentioned correct or wrong.



Common Mistake Related to Question 3:
Very common Answer is 2 which is not correct. Why? Check .lib file.

Common Mistake Related to Question 4:
Solution is very simple - Connect both the select line or say short both the select line. But common mistake - we miss to make changes in the labelling.


Common Mistake Related to Question 5
  • Candidates become confuse between Decoder method and Mux method. :)
  • Most of the Candidates confuse at the labelling part.

Common Mistake Related to Question 7
Normally, in college text books (or say basic Digital Electronics Books) - internal circuit is based on AND gate. So, we start with the AND gate based circuit of MUX and then convert respective AND gate with MOS. But actually, Interviewer need to know Pass Transistor or say Transmission gate based MUX. :)

Common Mistake Related to Question 8
Usually, we gave single answer but actually it depends how we have implemented MUX. Means using CMOS or Only NMOS/PMOS.

Common Mistake Related to Question 9
Usually we draw a single circuit, which we have learnt. But we miss to draw truth table and then implement using MUX. If you use this approach - you can implement any logic gate using MUX. Interviewer, also see your approach and need to understand whether you know the concepts or method or you have just mugged it.


Happy Learning and Best of Luck.

Friday, February 9, 2018

Logic Level & Noise Margin


Today, we will talk about the logic levels and what’s all this. I came across several students and realize that they are struggling big time to understand the Logic level, Input-output logic level and all.


Let’s start with above known logic level diagram. Here, you can see that range of signal for Logic 0 is 0V to 1V and similarly for Logic 1 – It’s 2V to 3V, Till this point, everyone is (should be) clear. But the moment I ask what’s between Logic 1 and Logic 0 – confusion start. Few says it’s Undefined region and few smart kid says – it’s Noise Margin. :) The moment I ask them to define or provide more insight about this Noise region (as per smart kid), none of them able to define it. :)

In this article, we will discuss about this region and more related concepts.

Remember, everything above is with respect to Positive Logic Level and same we will discuss through out this article. To understand what’s Positive Logic Level and Negative Logic Level – please refer Digital Basic (Logic Gates – Part a).

Voltage Logic Level (Input/Output)



Let's try to understand the Logic Level at the Input and Output of a Gate.

Logic Level at the input of the Gate is known as Input Logic Level and corresponding voltage range as:
  • Logic 1: Start from VIH (Minimum Input Voltage for Logic High) and Ends at VDD
  • Logic 0: Start from VSS and Ends at VIL (Maximum Input Voltage for Logic Low)

Logic Level at the output of the Gate is known as Output Logic Level and corresponding voltage range as:
  • Logic 1: Start from VOH (Minimum Output Voltage for Logic High) and Ends at VDD
  • Logic 0: Start from VSS and Ends at VOL (Maximum Output Voltage for Logic Low)

Below Figure, can help you to understand what I am talking about...


Now, as a difference, you can see both (Input and Output Logic levels) have voltage range for Logic 1 & Logic 0. So Next question is:

  • Are VOH = VIH and VOL = VIL ??
  • What's the relationship between different voltage level? ??

You have to justify your answer with proper reason. Let me try from my side :) with logical explanation.


In above fig, 2 NAND gates (1 & 2) are connected back to back. Let’s consider both NAND gates are 100% similar. If, NET Delay is Zero, Our Expectation is :: Any signal at the output of “Gate1 with Logic 1” should be identify as “Logic 1 at the Input of Gate2”. Same goes with Logic 0 also. Let's try to understand with example (if helps you to understand more clearly).

Scenario 1: VOH < VIH ; VDD = 5V, VOH = 3V, VIL = 1V, VIH = 4V

  • Output Logic 1
    • Voltage range of Output Logic 1 is between 3V to 5V.
    • It means any signal with a voltage value between 3V and 5V is consider as Logic 1 at the output pin of Gate1.
  • Input Logic 1
    • Voltage range of Input Logic 1 is between 4V to 5V.
    • It means any signal with a voltage value between 4V and 5V is considered as Logic 1.
    • Any signal below 4V is NOT considered as part of Logic 1.

Now, assume that a signal coming out from Gate 1 has voltage = 3V. It’s consider as part of Logic 1 for Gate 1 but when this signal propagate and reach at input of Gate 2, it will be nowhere (Means neither 1 nor 0 because voltage range of Logic 1 start from 4V and voltage range of Logic 0 ends at 1V).
So, in this Ideal scenario (Ideal means No Net Voltage Drop), to capture the Logic 1 at the input of Gate 2, Output voltage of Gate 1 for Logic 1 should have below condition.

VOH ≥ VIH

Scenario 2: VOL ≥ VIL ; VSS = 0V, VOL = 2V, VIL = 1V, VIH = 4V

  • Output Logic 0
    • Voltage range of Output Logic 0 is between 0V to 2V.
    • It means any signal with a voltage value between 0V and 2V is consider as Logic 0.
  • Input Logic 0
    • Voltage range of Input Logic 0 is between 0V to 1V.
    • It means any signal with a voltage value between 0V and 1V is considered as Logic 0.
    • Any signal above 1V is not considered as part of Logic 0.

Now, assume that a signal coming out from Gate 1 has voltage = 2V. It’s consider as part of Logic 0 for Gate 1 but when this signal propagate and reach at input of Gate 2, it will be nowhere (Means neither 1 nor 0 because voltage range of Logic 0 ends at 1V and voltage range of Logic 1 start from 4V).
So in this Ideal scenario (Ideal means No Net Voltage Drop), to capture the Logic 0 at the input of Gate 2, Output voltage of Gate 1 for Logic 0 should have below condition.

VOL ≤ VIL

On the basic of above 2 scenarios, I can easily summarize that ...

VOH ≥ VIH
VOL ≤ VIL

In above example, we have discussed all between 2 different gates (Output logic of 1st Gate and Input Logic of 2nd) and you may be thinking on the basis we summarize this relationship (because original question was Input Logic Vs Output Logic of Same Gate :)). Just in case, if that’s your confusion – then check again – I have mentioned above that both gates are identical (so it means input logic levels of 2nd Gate == Input Logic Levels of 1st Gate also. :):) ).

On the basis of this, if anyone give you below 4 options and ask you which one is the right set of Input-Output Logic combination – I am sure , it will be easy to find out. (I am not going to give answer, you can write in comment section with reason :) ).


Till now, we considered the Ideal scenario (NO voltage drop across NET) But as you know nothing is ideal in this world, so keeping that in mind – our conditions changes and in real world condition will be ….

VOH > VIH
VOL < VIL


Now, If I want to represent this In a single diagram – below is the representation.


Okay, so till now we are able to understand different nomenclature, Like VOH , VIH , VOL , VIL in logic level, their importance and relationship between them.

Now, if you remember, our discussion started with 2 things – Undefined Region and Noise Margin...

Noise Region and Undefined Region



To understand the Noise Margin, you have to first understand what a "Noise" can do! In general, we can categorize Noise in 2 ways
  • Noise Inside the Gate
    • Noise inside the Gate already taken care during simulation of Gate & only after that we define (or conclude) VOH, VOL
  • Noise Outside the Gate
    • This Noise effects the signal which is traveling from the output pin of a gate to input pin to other gate

Let's talk about the Noise which developed or generated because of environment and effect Signal traveling between input and output pin of a Gate.

In general, Noise is Random in nature and you can’t model it exactly (at least the source of Noise :)). This Noise can be positive or negative in nature (when I am saying positive/negative it means with respect to zero reference level). It means if there is a output signal of 4V and suddenly a positive noise of 0.5V come, signal convert into 4.5V. Similarly, if Negative Noise of 0.5V come, output signal convert into 3.5V.

Let’s consider a scenario,

For Gate 2: VOH = 4V, VIH = 3.5V,
Output signal from the 1st Gate is of 4V.

Now, question is what should be the maximum Noise value (in terms of voltage), so that even after noise 2nd Gate identify Logic 1 correctly ?

As, we have discussed Noise can be Positive and Negative also –

If Noise is Positive then it’s going to add in output voltage .. Means output is going to increase above 4V, which is okay for 2nd gate because for 2nd Gate Voltage range start for Logic level 1 is above 3.5V.

If Noise is Negative then it’s going to reduce output voltage .. It means output is going to decrease & value will be less the 4V. If that’s the case we have to understand that Voltage range for Input logic High (1) start from 3.5V. Any signal less then 3.5V is not considered as Logic 1 signal at the input of Gate2. So, I can easily say that in this scenario, Maximum allowable Noise in negative side is 4V – 3.5V = 0.5V or you can say that VOH – VIH. This difference we are saying NOISE MARGIN for LOGIC HIGH.

NOISE MARGIN HIGH LOGIC = VOH – VIH

With the similar explanation, I can easily say that in case of Logic 0, any noise which increases the voltage of output logic signal beyond Max input Voltage for Logic 0, consider as not acceptable Noise. So, any Noise between VOL and VIL is acceptable for Logic 0. Means..

NOISE MARGIN LOW LOGIC = VIL – VOL

Okay, so if this is the NOISE Margin, what’s the Undefined Region ? Answer is simple – Remaining portion is considered as Undefined Region. :)


I know, now you may be thinking that above description is good when we talk in terms of Input Vs Output Logic Level. But If we talk only about Logic level (Individual), then how can we defined the region between “Min Voltage for Logic 1” and “Max Voltage for Logic 0”.

Any signal with in this range is considered as uncertain, and no one is going to give you guarantee how other Gate (input Gate) would interpret such signal because that depends on Input level of 2nd gate :). Now, if your other gate (gate which is going to receive this signal at input port) has wider voltage range for Logic 1 or 0, most of your signals between uncertain range can be consider either Logic 0 or Logic 1.

So, This region is considered as Uncertain Region. It means signal in this region can be consider as Logic 0 or 1 depends on Logic level Range of Next stage Input gate. I will not say that it’s Undefined Region because undefined means – It's neither be 0 nor 1.

Note: "Either be 0 or 1" is completely different from "Neither be 0 nor 1".

If you are not clear with my statement – let's try to understand with one more example of say scenario.:).


In above circuit, output of NAND Gate“1” is connected with 2 another NAND Gates. All NAND gates are different.

Input Logic Level of NAND 2:
Logic 0 – From 0V to 2V
Logic 1 – From 3V to 5V

Input Logic Level of NAND 3:
Logic 0 – From 0V to 1.5V
Logic 1 – From 3.5V to 5V.

Output Logic Level of NAND 1:
Logic 0 – From 0V to 1V
Logic 1 – From 4V to 5V.

Let’s assume At a particular instance, the output signal voltage at NAND Gate 1 is 3.2V. As per Output voltage levels (as per our above discussion), it’s in Uncertain Area. When this signal propagate through wire & reaches at
  • NAND Gate 3
    • It’s below Voltage range for Logic level 1 (3.5V to 5V)
    • And above Voltage range for Logic level 0 (0V to 1.5V)
    • So this signal is considered as part of UNDEFINED Region.
  • NAND Gate 2
    • It’s above Voltage range for Logic level 1 (3V to 5V)
    • So, this signal is considered as part of Logic 1.

So, it means Same voltage can be part of Undefined Region and also as part of Logic Level 1. Same case can happen for Logic 0 also.

In Summary:


  • Range between VOH and VOL can be consider as uncertain range with respect to that gate.
  • A range between VIH and VIL is considered as undefined region for that particular gate.
  • Undefined region is with respect to Input Signal range.
  • Uncertain Region is with respect to Output Signal Logic Range
  • Noise Margin always with respect to Input and Output Logic range. :)

VOH > VIH
VOL < VIL
NOISE MARGIN HIGH LOGIC = VOH – VIH
NOISE MARGIN LOW LOGIC = VIL – VOL


I hope this article will help you to understand the Logic Level concepts in much more depth and help everyone (Specially Students) to understand the concepts :).


HAPPY LEARNING

Monday, January 22, 2018

Unateness of Complex Circuit: Timing Arc


STA & SI:: Chapter 1: Introduction
1.1a 1.1b 1.1c 1.2a 1.2b
INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

Unateness of Complex Circuit: Timing Arc:


In last article (Unate: Timing Arc), we have discussed about the unateness property of Timing arc with respect to Logic gates. In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

In this article, we are trying to extend timing arc concepts from simple "Logic gate" to complex combinational circuit. For that first we need to understand how we can calculate or figure out the overall unateness of a complex circuit or say a system. To understand this, We start with few standard logic functions like AOI (AND-OR-Inverter) which is not that complex but help us to understand the concept of unateness in system.

To understand the Timing Arc concept for combinational circuit, we should know how Timing Arc of a system calculated. Let's take an example to understand this.



In the above circuit, you can see that there are 2 type of Timing Arc (Net Timing Arc and Cell Timing Arc).
  • Net Timing Arc is always Positive Unate.
  • Cell Timing Arc, we have already discussed in previous Article. (Unateness of Logic Gates )
    • NAND Gate - Negative Unateness
    • NOT Gate - Negative Unateness
    • NOR Gate - Negative Unateness

Note: To know more about the Unateness of Inverter, please read Article

So, If I want to understand the behaviors of signal at Y with respect to A (remember only A, Not with respect to other pins like B & C), then we can conclude as
  • Rising Input at A - Falling Output at Y or No Change.
  • Falling Input at A - Rising Output at Y or No Change.


If you want to cross check this, there are several ways but I am going to explain (or say cover here) 3 ways.
  1. Truth table Method
  2. Circuit Method
  3. Function Method

1) Truth Table Method

Below is the Truth table ("Table_1") of AND-OR-INVERTER circuit of "Figure_1". I have highlighted all cases when A changes from 0 to 1 (keeping all other inputs constant at a time), you can see that output either "Not Changing" or changing from 1 to 0. You can try reverse case also (A changes from 1 to 0).


So in summary, I can say that it's a Negative Unate at Y with respect to A. I am not describing much about this method because we already studied this in previous Article (Unate: Timing Arc)

In a similar way, if you will try with respect to B, you will find similar result (Negative Unate at Y with respect to B).

2) Circuit Method

I am sure, you might be thinking about the shortest way to figure out the Unateness between 2 input-output combination. Because using the Truth table is not Feasible every time and it's Time consuming also. Lets try to understand the circuit method.

Below table (Table_2) help you to understand the Unateness from a Overall system point of view. It's very simple. I have explained with respect to 2 System (Output of 1st system become input of Second system). Using this table, we will try to understand the overall unateness of any complex circuit.


Now, if above table (Table_2) is clear - let's try to understand how this table help us in AOI case (AND-OR-INVERTER) (Figure_1).
  • A to u1   - System 1   - Negative Unate (AND gate)
  • u1 to u2   - System 2   - Positive Unate (Wire/Net)
  • u2 to u3   - System 3   - Negative Unate (NOT gate)
  • u3 to u4   - System 4   - Positive Unate (Wire/Net)
  • u4 to Y   - System 5   - Negative Unate (NOR Gate)

So now, if you will see across different Systems (from 1 to 5), you can see that overall unateness is Negative Unate.

3) Function Method

How will you identify the unateness in case you dnt have circuit, you only have equation (Boolean Equation) of circuit or design? Again, If I will ask you that draw a circuit or create a truth table, then I am sure, you will try to skip it. But there is a solution of that. :)

For that, below definitions can help you to determine unateness of any variable of Function.
  • f is “positive unate” function in a dependent variable "x" if x’ does not appear in the sum-of-products representation.
  • f is “negative unate” in a dependent variable "x" if x does not appear in the sum-of-products representation.
  • f is “non unate” (sometime known as biunate in switching theory) in a dependent variable "x" if you can not write a sum-of-products representation without appearing x and x' both together. Means both be the part of SOP.

For example 1: F(w, x, z)= wx + w’z’
In the above function, if you try to implement above definition, you can easily figure out that
  • Positive unate with respect to x
  • Negative Unate with respect to z
  • Non-unate with respect to w

For example 2: F(w, x, z)= wx + w’z’
Now, question is what will be with respect to y.
If you will see the equation, it's very much clear that even if you give rising edge or falling edge at "y", output is not going to change. That's means it's neither Negative unate nor Positive unate nor Non-Unate. I am sure, now you may be confuse that what's this? :) Right now, I am leaving this as a open topic of discussion for later on. You can comment about these type of variables.

Now, if above function definition is clear - let's try to understand how these can be implemented in AOI case (AND-OR-INVERTER) (Figure_1).

Figure_1 can be written in the form of equations as: Y = ((A.B) + C)'

Let's open in simplified SOP form.

Y = ((A.B) + C)'
  = ((A.B)').(C)'
  = (A'+B').C'
  = A'C' + B'C'

Now, you can easily say -
  • Y is Negative unate with respect to A
  • Y is Negative Unate with respect to B
  • Y is Negative Unate with respect to C

In Summary: We can use any method as per our convenience to see the unateness of a system or circuit. Most of the time, this is already part of Lib file, but to understand the tool behavior, we should have these understanding.

In next article, we will discuss Unateness of OAI (OR-AND-Inverter), MUX and few other complex circuit.

Monday, January 1, 2018

AOI (AND-OR-INVERTER) Cell

AOI also known as AND-OR-Inverter.

AND-OR-Invert (AOI) logic or say gates are two-level logic functions constructed from the combination of one or more AND gates followed by a NOR gate. If we construct AND, OR and NOT gate separately, Number of transistor in AOI gates are less.

You might be thinking why need individual logic gate, why can't we implement it using just 2 AND gate and 1 NOR gate. Yes, you are right. But now think from CMOS point of view. In CMOS, we can implement AND gate using 1 CMOS NAND gate and 1 Inverter. It means above 2 AND gate changes into 2 NAND and 2 Inverter. I hope this explanation rang a bell in your mind. If not, keep patience (this is only I am going to explain in this article :) ).
Let's take an example and try to understand it.

For example: 2-2 AOI gate: ((A.B) + (C.D))'

Let's see how this function be implemented using logic gates (separately) Vs AOI cells.

Using Individual NAND, NOT and NOR Gate:
First we have to change the function as per logic gates availability. Y== ((A.B) + (C.D))' == (((A.B)')' + ((C.D)')')'


Function (((A.B)')' + ((C.D)')')' can be implemented as:
  • NAND Gates:
    • 2 NAND gates: 1st for (A.B)' and 2nd for (C.D)' (Assume X=(A.B)' and Y=(C.D)')
    • 1 NAND gate uses 2 PMOS transistor and 2 NMOS transistor.
    • So, total Transistors in 2 2-input NAND gate are 8 Transistors.
  • Inverter:
    • 2 Inverter: 1st (X)' and 2nd for (Y)'
    • 1 Inverter uses 1 PMOS and 1 NMOS
    • So, total Transistors in 1 Inverter are 2 Transistors.
  • NOR Gates:
    • 1 NOR Gate: (X' + Y')'
    • 1 NOR gate uses 2 PMOS transistor and 2 NMOS transistor.
    • So, total Transistors in 1 2-input NOR gate are 4 Transistors.

Total Transistor in case of Individually implementing ((A.B) + (C.D))' = 14 Transistor.

CMOS Representation of above function is given below.


Using AOI logic gates.
Implementation using AOI cells are very easy. In this case, we are not suppose to change the function. Y == ((A.B) + (C.D))'


Below diagram can help you to understand how cells can implement using CMOS. In this case, total Transistor require are 8 Transistor. If you are not able to understand this part (I am sure you need to refresh your concept for CMOS circuit).


From above explanation, I am sure you are now in position to understand the importance of AOI cells. These cells are so important that in Standard cell library, you can easily find these cells (as other logic gates). So in short, I can say that these are also part of STANDARD Cells (So don't assume that only NAND, AND, OR, Buffer, Inverter, XOR, XNOR are Standard cells).

In a similar fashion, you can take any example and try to understand how many transistors are required in case of implementing that function in AOI form. This type of questions are very common during Interview or Written test.

Less number of Transistors for implementing a particular logic function helps in multiple ways. Like
  • Increased speed: Less transistor means less delay, means fast response time.
  • Reduced Power: Less number of transistor means less power consumption.
  • Smaller area: Less number of transistor means less area consumption.
  • Potentially lower fabrication cost: Fabrication cost is also less because of less number of manufacturing of transistor.

You can also understand OAI cells in similar way OR if you are not able to .. then wait for my Article. :)

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