## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Monday, January 22, 2018

### Unateness of Complex Circuit: Timing Arc

 STA & SI:: Chapter 1: Introduction 1.1a 1.1b 1.1c 1.2a 1.2b INTRODUCTION Timing Arc Unate: Timing Arc Unateness of Complex Circuit: Timing Arc LIB File syntax for Logic Gates: Timing Sense LIB File syntax for Complex Circuit: Timing Sense

### Unateness of Complex Circuit: Timing Arc:

In last article (Unate: Timing Arc), we have discussed about the unateness property of Timing arc with respect to Logic gates. In the Timing Library, "Timing Arc information" is stored with the syntax "timing_sense".

In this article, we are trying to extend timing arc concepts from simple "Logic gate" to complex combinational circuit. For that first we need to understand how we can calculate or figure out the overall unateness of a complex circuit or say a system. To understand this, We start with few standard logic functions like AOI (AND-OR-Inverter) which is not that complex but help us to understand the concept of unateness in system.

To understand the Timing Arc concept for combinational circuit, we should know how Timing Arc of a system calculated. Let's take an example to understand this.

In the above circuit, you can see that there are 2 type of Timing Arc (Net Timing Arc and Cell Timing Arc).
• Net Timing Arc is always Positive Unate.
• Cell Timing Arc, we have already discussed in previous Article. (Unateness of Logic Gates )
• NAND Gate - Negative Unateness
• NOT Gate - Negative Unateness
• NOR Gate - Negative Unateness

So, If I want to understand the behaviors of signal at Y with respect to A (remember only A, Not with respect to other pins like B & C), then we can conclude as
• Rising Input at A - Falling Output at Y or No Change.
• Falling Input at A - Rising Output at Y or No Change.

If you want to cross check this, there are several ways but I am going to explain (or say cover here) 3 ways.
1. Truth table Method
2. Circuit Method
3. Function Method

### 1) Truth Table Method

Below is the Truth table ("Table_1") of AND-OR-INVERTER circuit of "Figure_1". I have highlighted all cases when A changes from 0 to 1 (keeping all other inputs constant at a time), you can see that output either "Not Changing" or changing from 1 to 0. You can try reverse case also (A changes from 1 to 0).

So in summary, I can say that it's a Negative Unate at Y with respect to A. I am not describing much about this method because we already studied this in previous Article (Unate: Timing Arc)

In a similar way, if you will try with respect to B, you will find similar result (Negative Unate at Y with respect to B).

### 2) Circuit Method

I am sure, you might be thinking about the shortest way to figure out the Unateness between 2 input-output combination. Because using the Truth table is not Feasible every time and it's Time consuming also. Lets try to understand the circuit method.

Below table (Table_2) help you to understand the Unateness from a Overall system point of view. It's very simple. I have explained with respect to 2 System (Output of 1st system become input of Second system). Using this table, we will try to understand the overall unateness of any complex circuit.

Now, if above table (Table_2) is clear - let's try to understand how this table help us in AOI case (AND-OR-INVERTER) (Figure_1).
• A to u1   - System 1   - Negative Unate (AND gate)
• u1 to u2   - System 2   - Positive Unate (Wire/Net)
• u2 to u3   - System 3   - Negative Unate (NOT gate)
• u3 to u4   - System 4   - Positive Unate (Wire/Net)
• u4 to Y   - System 5   - Negative Unate (NOR Gate)

So now, if you will see across different Systems (from 1 to 5), you can see that overall unateness is Negative Unate.

### 3) Function Method

How will you identify the unateness in case you dnt have circuit, you only have equation (Boolean Equation) of circuit or design? Again, If I will ask you that draw a circuit or create a truth table, then I am sure, you will try to skip it. But there is a solution of that. :)

For that, below definitions can help you to determine unateness of any variable of Function.
• f is “positive unate” function in a dependent variable "x" if x’ does not appear in the sum-of-products representation.
• f is “negative unate” in a dependent variable "x" if x does not appear in the sum-of-products representation.
• f is “non unate” (sometime known as biunate in switching theory) in a dependent variable "x" if you can not write a sum-of-products representation without appearing x and x' both together. Means both be the part of SOP.

For example 1: F(w, x, z)= wx + w’z’
In the above function, if you try to implement above definition, you can easily figure out that
• Positive unate with respect to x
• Negative Unate with respect to z
• Non-unate with respect to w

For example 2: F(w, x, z)= wx + w’z’
Now, question is what will be with respect to y.
If you will see the equation, it's very much clear that even if you give rising edge or falling edge at "y", output is not going to change. That's means it's neither Negative unate nor Positive unate nor Non-Unate. I am sure, now you may be confuse that what's this? :) Right now, I am leaving this as a open topic of discussion for later on. You can comment about these type of variables.

Now, if above function definition is clear - let's try to understand how these can be implemented in AOI case (AND-OR-INVERTER) (Figure_1).

Figure_1 can be written in the form of equations as: Y = ((A.B) + C)'

Let's open in simplified SOP form.

Y = ((A.B) + C)'
= ((A.B)').(C)'
= (A'+B').C'
= A'C' + B'C'

Now, you can easily say -
• Y is Negative unate with respect to A
• Y is Negative Unate with respect to B
• Y is Negative Unate with respect to C

In Summary: We can use any method as per our convenience to see the unateness of a system or circuit. Most of the time, this is already part of Lib file, but to understand the tool behavior, we should have these understanding.

In next article, we will discuss Unateness of OAI (OR-AND-Inverter), MUX and few other complex circuit.

## Monday, January 1, 2018

### AOI (AND-OR-INVERTER) Cell

AOI also known as AND-OR-Inverter.

AND-OR-Invert (AOI) logic or say gates are two-level logic functions constructed from the combination of one or more AND gates followed by a NOR gate. If we construct AND, OR and NOT gate separately, Number of transistor in AOI gates are less.

You might be thinking why need individual logic gate, why can't we implement it using just 2 AND gate and 1 NOR gate. Yes, you are right. But now think from CMOS point of view. In CMOS, we can implement AND gate using 1 CMOS NAND gate and 1 Inverter. It means above 2 AND gate changes into 2 NAND and 2 Inverter. I hope this explanation rang a bell in your mind. If not, keep patience (this is only I am going to explain in this article :) ).
Let's take an example and try to understand it.

For example: 2-2 AOI gate: ((A.B) + (C.D))'

Let's see how this function be implemented using logic gates (separately) Vs AOI cells.

Using Individual NAND, NOT and NOR Gate:
First we have to change the function as per logic gates availability. Y== ((A.B) + (C.D))' == (((A.B)')' + ((C.D)')')'

Function (((A.B)')' + ((C.D)')')' can be implemented as:
• NAND Gates:
• 2 NAND gates: 1st for (A.B)' and 2nd for (C.D)' (Assume X=(A.B)' and Y=(C.D)')
• 1 NAND gate uses 2 PMOS transistor and 2 NMOS transistor.
• So, total Transistors in 2 2-input NAND gate are 8 Transistors.
• Inverter:
• 2 Inverter: 1st (X)' and 2nd for (Y)'
• 1 Inverter uses 1 PMOS and 1 NMOS
• So, total Transistors in 1 Inverter are 2 Transistors.
• NOR Gates:
• 1 NOR Gate: (X' + Y')'
• 1 NOR gate uses 2 PMOS transistor and 2 NMOS transistor.
• So, total Transistors in 1 2-input NOR gate are 4 Transistors.

Total Transistor in case of Individually implementing ((A.B) + (C.D))' = 14 Transistor.

CMOS Representation of above function is given below.

Using AOI logic gates.
Implementation using AOI cells are very easy. In this case, we are not suppose to change the function. Y == ((A.B) + (C.D))'

Below diagram can help you to understand how cells can implement using CMOS. In this case, total Transistor require are 8 Transistor. If you are not able to understand this part (I am sure you need to refresh your concept for CMOS circuit).

From above explanation, I am sure you are now in position to understand the importance of AOI cells. These cells are so important that in Standard cell library, you can easily find these cells (as other logic gates). So in short, I can say that these are also part of STANDARD Cells (So don't assume that only NAND, AND, OR, Buffer, Inverter, XOR, XNOR are Standard cells).

In a similar fashion, you can take any example and try to understand how many transistors are required in case of implementing that function in AOI form. This type of questions are very common during Interview or Written test.

Less number of Transistors for implementing a particular logic function helps in multiple ways. Like
• Increased speed: Less transistor means less delay, means fast response time.
• Reduced Power: Less number of transistor means less power consumption.
• Smaller area: Less number of transistor means less area consumption.
• Potentially lower fabrication cost: Fabrication cost is also less because of less number of manufacturing of transistor.

You can also understand OAI cells in similar way OR if you are not able to .. then wait for my Article. :)