## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Sunday, June 6, 2021

### Latch Based Timing Analysis - Part 2 (Capture and Launch Edges)

In the last article (Latch Based Timing Analysis - Part 1) of this series, we have discussed general differences and correlation between Latch and Flipflop from Timing analysis point of view. We have discussed, how in case of Latches, Edges are also important and what's the significance of those edges.
Just to summarize or say refresh your memory, below are few points along with respective figure.

1. Latches start sampling data from the Start Edge respective to Enable level. Means, if Latch is Positive level - respective Start edge is Rising edge (as showing in figure)
2. Latches continue sampling data at Enable Levels (either Positive or Negative)
3. Latches stop sampling data at the End Edge respective to Enable Level. If Latch is Positive level - respective stop edge is Falling edge (as showing in figure)
4. In case of 2 Latch based circuit (one is Launch Latch and other as Capture Latch), if we want to Launch data at one level (assume at X1 - as in fig) from one Latch and capture the data at other Level (assume at X2 - as in fig), It's important to understand first/last edge of Launch & Capture latch(Please refer last article for detail)

If above concepts are clear, lets try to understand the circuit & respective waveform based on 3 latches. Because that's very important to understand this concepts.

In Above figure, there are 3 Latches (L1, L2 & L3) connected back to back. Lets assume L1 launches the data at the rising edge. There are 2 different paths between the latches and that's the reason it's reaching at L2 at 2 different time. Blue one is with respect to shortest path and Red one is with respect to longest path. If you have noticed that both the datas are reaching after 10ns (sometime after L2 latch become enable) but as Latch is level triggered and L2 is enabled at this time. So, L2 capture the data at D pin and launches it to next timing path at the same moment (not considering the delay of latch in this example).

Important point to understand at this stage - data reaching at L2 at 2 different time (depending on data path between L1 and L2), the moment data reaches at L2, it will automatically launched by L2 (because L2 is enable/transparent at that time). So, now you can see that launching time/point for data is different by L2.

If combinational circuit between L2 and L3 also have smallest and longest path - means data again have 2 combinations
• Red data with shortest path
• Red data with longest path
• Blue data with shortest path
• Blue data with longest path
but for simplicity purpose, we have only represented 2 set of data - Red data with Longest path and Blue data with shortest path. You can draw picture with other 2 combination and try to understand the yourself. Consider this an exercise for you :).

Data launches by L2, reaches at 2 different time at L3 (as shown in figure). Since, L3 is enabled at that time, it will again launch it at the same time. If you have noticed the Time line - Data launched by L1 at 0ns can easily launched by L3 (even in worst case) at 25ns.

Now, lets try to undestand what's going to happen if same combinational circuit is present between the Flipflop.

Flip-flop F1 is going to launch the data at 0ns, because of presence of smallest and longest path, data is reaching at F2 at 2 different time and after 10ns. Since, F2 is a positive edge triggered flip-flop & data were not present in either of case before 10ns, data has to wait for next positive edge at F2.

Next positive edge is going to be at 20ns and irrespective of data travelling any path (smallest path or longest path) between F1 and F2, F2 is going to capture it at 20ns and launch the data for next Timing path between F2 and F3.

Again data travel through shortest and longest data path and reaches at F3 at 2 different time. As per the figure, again you can see data is not reaching before 30ns (which is the next rising edge point at F3), so data has to wait for next rising edge which is at 40ns. So, F3 is going to capture the data and launches it at 40ns.

So, In summary, I can say - Data launched by FF1 at 0ns, launched by FF3 (even in worst case) at 40ns.

This much understanding is sufficient for this Article. At least, now you can see how much time we are saving just replacing the Flip-flop with latches and how our circuit become fast by using latches. But on the other side, complexity also increases. In case of Flipflop, it's very simple that Lauch and Capture edge is going to be at edges and we have to make sure that data reaches before capture edges but in case of Latch, a lot of othe concepts comes into the analysis. and Don't worry - we are going to discuss those concepts in this series of Articles :).

Stay Tune for next article.

#### 1 comment:

1. These articles are great, when do you think you will be able to put up the remaining articles in this series?