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VLSI BASICS:

Timing Analysis:

  • Design Constraint



  • Timing Models



  • Clock:

    Signal Integrity:

    Parasitic Extractions.

    Physical Verification:
    • Antenna Effects
      • What is antenna effects?
      • Design Solution to reduce the antenna effect.
        • Jumper instertion
        • Diode insertion.
      • Antenna Rules
        • Caliber
        • Magma
        • Synopsys
    • Conformal Dielectric
    • Process Variation
      • Type of Process variation
        • Random Variation
        • Systematic Variation
        • Inter-die or Die-to-Die variation
        • Intera-die or Within-Die Variation
      • Modelling of Variation
    Appendix:

      29 comments:

      1. the site is really very good.. gr8 job....
        can u please write about metastability and frequency dividers....

        ReplyDelete
      2. Wonderful website and very helpful. Thanks to everybody involved in this, specially the lecturers, Thank you Sir:)

        ReplyDelete
      3. really grt work ... description is in really easy and understandable language waiting for more posts.... :)

        ReplyDelete
      4. Very exciting and helpful.. Thanks!

        ReplyDelete
      5. god bless u 4 this wonderful job
        god may accomplice all ur desires
        thanks :)

        ReplyDelete
      6. from where did u copy ???
        tell me book asap ghade :@

        ReplyDelete
      7. great articles!
        Is there an option to download all articles as pdf files?

        ReplyDelete
      8. sir ,
        will you please add some of the cells in library like well tap , end cap , de cap ......... cells why they are used in the design and their internal structure . that will be very useful to us.

        ReplyDelete
        Replies
        1. Sure -- I will try my best to do so.

          Delete
      9. Excellent and very useful site. congratulations for the team site.

        ReplyDelete
      10. Hi Please upload a ASIC Physical Design (PD) Questions with answers that can be asked in Interviews.

        Rajesh

        ReplyDelete
      11. And If hold time is Th for a flip flop and if data is not stable **** Before ****8 Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.

        ReplyDelete
      12. May God Bless you. Your blog has been of immense help.

        ReplyDelete
      13. thank you very much. The information is very useful

        ReplyDelete
      14. sir pls send me some usefull documents on chapter 7 few vlsi terminolgy .... at piyuw1791@gmail.com

        ReplyDelete
      15. Please correct the Verilog in both examples below. Explain in each example what the problem is.
        Example 1
        always @ (s1)
        begin
        if (s1)
        output1=a + b;
        else
        output2=b + c;
        end
        Example 2
        assign data2 = in2 ;
        always @ (clock)
        data2 <= in1

        ReplyDelete
        Replies
        1. Hi Ramesh,
          Somehow not able to understand your comment.

          Delete
      16. can u please expain the soc flow in one of your blog?

        ReplyDelete
        Replies
        1. I am not getting time these days. Busy in office work. I will update soon.

          Delete
      17. AWESOME SIR
        Please suggest hiring freshers VLSI companies.
        thanks

        ReplyDelete
      18. Please start posts on scripting languages used in VLSI industry like Tcl, Perl, SKILL

        ReplyDelete
      19. your site is a bible for vlsi

        ReplyDelete
      20. If someone is using icc tool for first time for physical verification from where he can get information about basic commands like get_cell, get_objects.....etc

        ReplyDelete
        Replies
        1. Manual of the tools.. :)

          Delete
      21. Fabulous work Sir...Great...
        Very few people are there who really share knowledge for free...
        Keep up the good work. Long Live!:)

        ReplyDelete

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