## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

# Manufacturing Effects: Introduction

 Chapter 3: Manufacturing Effects and Their Modeling 3.1 3.2a 3.2b 3.3a 3.3b 3.3c 3.4 Introduction Effect Of Etching Process Effect Of Etching Process Chemical Mechanical Planarization Importance Of CMP process Dishing & Erosion (CMP effects) Lithography 3.5a 3.5b 3.5c 3.5d 3.5e 3.5f 3.5g Metal Width Variation (Type:1-2) Metal Width Variation (Type3) Metal Width Variation (Type:4-5) Metal Width Variation (Type6) Metal Width Variation (Type7) Metal Width Variation (Type8) Metal Width Variation (Summary)

Cbest and Cworst corners are used to model interconnects as being capacitance dominated to calculate the stage delay and RC-best and RC-worst are used to compute the Interconnect delay when both resistance and capacitance of the wire is significant.

There are following main parameters which can affect the wire resistance and capacitance.

1. Width of metal
2. Length of metal
3. Thickness of metal
4. Dielectric thickness

"Thickness of metal" and "Dielectric thickness" is not a part of routing process. Means these are out of designer control (Please let me know if I am wrong here). So from designer perspective Width and Length of the metal is important.

So, we can say that on the basis of width and length of metal net/wire in a particular design, we can figure out which one is resistance dominant or capacitance dominant.
Thickness/Dielectric thicknesses are part of manufacturing parameters. Even designer can control width of wire, they have some limitations in choosing the width. They can’t draw any wire less then min_width (of particular layer) and similarly 2 metal wires can’t be placed closer then min_space (of particular layer). The reason of these limitations are the "Manufacturing effects".
It’s the right time to understand the manufacturing effects and for that, we have to understand the manufacturing process (Means - How are interconnects fabricated?). I am not going to discuss the complete fabrication process here but I will try to give you a brief idea only about interconnects fabrication process through the pictorial view.
Here is the sample which we are going to build.

On the basis of different steps, I will try to explain you different Interconnect variations.

Above process and final stack diagram is as per ideal scenario, but in reality because of several manufacturing / interconnect variations, the stack diagram would be something similar to …

Note: Above diagram is not very good but I have tried my best to cover most of the defects.

Now, you can notice that there are following parameters which are effecting most by the fabrication process which can directly impact our capacitance and Resistance values.

1. Thickness of Metal Wire
2. Thickness of Dielectric
3. Width of Metal
4. VIA thickness and width (It impact VIA resistance)

I am sure, now you are curious to know

• The Source/Reason of these variations and
• How can we minimize these? What are the different steps/precautions we should follow, so that impact should be minimal?
• If we can’t ignore these variations, can we model these somehow and take care during designing the layout.
• Many more ….

I am not sure whether I can help you in understanding 100%, but I will try my level best.
Before I will explain these things – I want to point out few important facts.

• These variations can’t be modeled 100%. Means you can model it upto a certain limit but even after that there are chances of some variations.
• These variations have a great dependency on the position of metal/via/dielectric with in Chip and wafer. So even if 2 metals are of similar type but placed at different position in chip, you can’t guarantee that variation effects are 100% identical. But if you have modeled correctly, then delta will be within a known limit.

Again you can ask why environment is unknown. And if it’s known, why can’t we model this. Science become so advance, why don’t we have solution of this till now? J

Simple ANS is No one can predict the future till now. So what will be the environment of a piece of metal wire in the full chip can’t be 100% defined. By the time you come to know it become too late. By the past experience, we usually try to define/model the environment but it’s very poor in quality in the starting of the design. Knowledge of environment become better as the design progress and 100% by the time chip is done. But once you come to know 100%, you can’t go back and model the variation and restart the whole design. And If I assume that you want to do that, then there is no guarantee that the end result will be same as you get last time.

Now even if you can control the 1st 4 steps, you can’t control the position of Full Chip on the wafer. And if you want to control that, then you have to design different chips for different position on the wafer (which is not the real solution).

So usually Foundry provides some recommendation (in the form of rules) + variation data (sometime in the form of Input files like technology files) on the basis of their previous experience. Now, it’s designer’s responsibility to decode/use that information as per their design and implement that during the design cycle.

About all those information which provide by the foundry, we will discuss in next few posts.

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