Static Timing analysis is divided into several parts:
- Part1 -> Timing Paths
- Part2 -> Time Borrowing
- Part3a -> Basic Concept Of Setup and Hold
- Part3b -> Basic Concept of Setup and Hold Violation
- Part3c -> Practical Examples for Setup and Hold Time / Violation
- Part4a -> Delay - Timing Path Delay
- Part4b -> Delay - Interconnect Delay Models
- Part4c -> Delay - Wire Load Model
- Part5a -> Maximum Clock Frequency
- Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
- Part 6a -> How to solve Setup and Hold Violation (basic example)
- Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
- Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
- Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
- Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
- Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
- Part 8 -> 10 ways to fix Setup and Hold Violation.
In a ASIC there are majorly two types of component. Flip-flop and other is Latches. Basically Here we will discuss about Latched based timing analysis.
Before this we should understand the basic differences between the latch based design and flip-flop based design.
- Edge-triggered flip-flops change states at the clock edges, whereas latches change states as long as the clock pin is enabled.
- The delay of a combinational logic path of a design using edge-triggered flip-flops cannot be longer than the clock period except for those specified as false paths and multiple-cycle paths. So the performance of a circuit is limited by the longest path of a design.
- In latch based design longer combinational path can be compensated by shorter path delays in the sebsequent logic stages.So for higher performance circuits deisgner are turning to latched based design.
Its true that in the latched based design its difficult to control the timing because of multi-phase clockes used and the lack of "hard" clock edges at which events must occur.
The technique of borrowing time from the shorter paths of the subsequent logic stages to the longer path is called time borrowing or cycle stealing.
Lets talk about this. Please See the following figure.
|Example of Latched based design.|
There are 4 latches (positive level sensitive). L1 and L3 are controlled by PH1 and L2 and L4 are controlled by PH2. G1, G2, G3 and G4 are combinational logic paths. For now assume a library setup time is zero for the latches and zero delay in latch data-path in the transparent mode.
Now if assume that if designs using edge-triggered flip-flops, the clock period has to be at least 8 ns because the longest path in G1 is 8 ns. Now as the clock pulse is 5ns , there is a voilation at L2. On the other hand, if the design uses latches , L2 latch is transparent for another 5ns and since the eighth (8th) ns is within the enabled period of L2, the signal along path1 can pass through L2 and continue on path2. Since the delay along path2 is 2 ns, which is short enough to compensate for the overdue delay of path1, this design will work properly. In other word we can say that path1 can borrow sometime (3ns) from the path2. Since the sum of path1 and path2 is 10ns, which is the required time of L3, there will be no voilation in either of the Latches.
For the same reason, path3 can borrow some time (1ns) from path4 without any timing violation.
Note: A latch-based design completes the execution of the four logic stages in 20 ns, whereas an edge-triggered based design needs 32 ns.
Lets see this in a more complex design. Its self explanatory.
|Example Of Timing Borrowing|
Just wanted to convey here that this Timing borrowing can be multistage. Means we can easily say that for a latched based design, each executing path must start at a time when its driving latch is enabled, and end at a time when its driven latch is enabled.
Few Important things:
- Time borrowing occur with in the same cycle. Means launching and capturing latches be using the same phase of the same clock. when the clocks of the launching and capturing latches are out of phase, time borrowing is not to happen. Usually it was disabled by EDA tools.
Time borrowing typically only affects setup slack calculation since time borrowing slows data arrival times. Since hold time slack calculation uses fastest data, time-borrowing typically does not affect hold slack calculation.
Few Important terminology:
Maximum Borrow time:
Maximum Borrow time is the clock pulse width minus the library setup time of the latch. Usually to calculate the maximum allowable borrow time, start with clock pulse width and then substract clock latency , clock reconvergence pessimism removal , library setup time of the endpoint latch.
Negative Borrow time:
If the arrival time minus the clock edge is a negative number, the amount of time borrowing is negative ( in other way you can say that no borrowing). This amount is know as Negative Borrow time.