## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Process Variation Other Topic

# How To Solve Setup and Hold Violation.. continue...

 Part1 Part2 Part3a Part3b Part3c Part4a Part4b Part4c Part5a Part 8

Static Timing analysis is divided into several parts:

In the last part/post we have discussed 2 examples with different specifications (Both net delay and Tck2Q were ideal means 0ns) and come to know that for Violation free Circuit, following conditions should be satisfied.

Min delay of Combinational path > Hold time of Capture FF.
Max delay of Combinational path < Clock Period - Setup time of Capture FF.

Clock Period >= Setup time + Hold time.

In this post we will discuss few more examples with more restrictions. Like

• What if we can’t reduce the Delay of Data path?

Let’s consider the following figure common to all examples until unless it’s specified

Example 3:

 Specification of the FF Circuit Setup Hold Clock period Tck2q delay Net Delay Combinational Logic Delay 3ns 2ns 10ns 0ns (Ideal) 0ns (Ideal) 5ns (can’t be further reduced).
On the basic of last post …let’s start with checking few conditions directly.
Clock Period Condition: (Satisfied)
Setup time +Hold time = 5ns
Clock period = 10ns
Clock Period > Setup time +Hold time (10> 5)

Min delay / Hold Condition:  (Satisfied)
Combinational Delay (5ns) > Hold time.
Means - NO HOLD VIOLATION

Max Delay / Setup Condition: (Satisfied)
Combinational delay (5ns) < Clock period (10ns) – Setup (3ns)
Means - NO SETUP VIOLATION.

This example is just to refresh your memories about the previous post.

Example 4:

 Specification of the FF Circuit Setup Hold Clock period Tck2q delay Net Delay Combinational Logic Delay 4ns 3ns 10ns 0ns (Ideal) 0ns (Ideal) 8ns (can’t be further reduced).

Clock Period Condition: (Satisfied)
Setup time +Hold time = 4ns+3ns = 7ns
Clock period = 10ns
Clock Period > Setup time + Hold time (10 > 7)

Min delay / Hold Condition:  (Satisfied)
Combinational Delay (8ns) > Hold time (3ns)
Means - NO HOLD VIOLATION

Max Delay / Setup Condition: (Not Satisfied)
Combinational delay (8ns) Is Not Less Than “Clock period (10ns) – Setup (4ns)”
Means - SETUP VIOLATION.

Since we can’t change this Combinational delay and also Setup time for the FF, so we have to think something else. J. Since we can’t touch the data path, we can try with clock path.

Flow of the data from FF1 to FF2:
• Let’s assume that you have added one buffer of T_capture delay in the clock path between the FF1 and FF2.
• Data is going to launch from FF1 at Clock Edge at 0ns and it will reach to FF2 after 8ns (combinational logic delay only).
• This data is going to capture at FF2 at Clock Edge at 10ns+T_capture. (because of Delay added by Buffer).
• As per the Setup definition, data should be stable 4ns (Setup time of FF2) before the Clock Edge at FF2 and in the above case clock edge is at t=T_capture+10ns.
So, for No Setup violation:

=> 8ns (Combinational Delay) < T_capture+10ns (clock period) – 4ns (Setup Time of FF2)
=> 12ns – 10ns < T_capture
=> T_capture > 2ns.

Let’s assume if my T_capture = 3ns. Then NO SETUP VIOLATION.

Now, recheck the Hold violation.
• At the FF1 – second set of data is going to launch at t=10ns and it will reach the FF2 in another 8ns, means at t=18ns.
• This second set of data is going to update/override the first set of data present at FF2.
• As per the Hold Definition, data should be stable till 3ns (Hold time of FF2) after the clock edge at FF2 (Which is at t=10ns+3ns=13ns – where 3ns is the T_capture).
• That means Data should be remain stable till t=13ns+3ns=16ns.
• In the above case the second set of data is going to override only after t=18ns. That means first set of data remain Stable till 16ns. Means NO HOLD VIOLATION.

Let me Generalize this concept:

I am sure, few people may have question that what will happen if we will add the buffer in the Launch path. Let’s discuss that. Please consider the following Diagram for this. In this Launch Clock path has a buffer with a delay of “T_launch” and Capture clock path has another buffer of delay “T_capture”.

 Specification of the FF Circuit Setup T_setup Hold T_hold Clock Period Clk_period Tck2q Delay 0 (Ideal) Net Delay 0 (Ideal) Combinational Logic Delay (b/w 2FFs) Td Launch Clock path Delay T_launch Capture Clock path Delay T_capture

Let’s understand the data flow from FF1 to FF2
• Data is going to launch from FF1 at Clock Edge at T_launch and it will reach to FF2 after Td (combinational logic delay only) that means t= “Td + T_launch”.
• This data is going to capture at FF2 at Clock Edge at “Clk_period + T_capture”
• As per the Setup definition, data should be stable “T_setup” (Setup time of FF2) time before the Clock Edge at FF2
• Means data should reach at FF2 before t= “Clk_period + T_capture – T_setup”.
So For NO SETUP VIOLATION:

=> T_launch + Td < Clk_period + T_capture – T_setup
=> Td < Clk_Period + (T_capture - T_launch) – T_setup

• At the FF1 – second set of data is going to launch at t= “Clk_Period + T_launch” and it will reach the FF2 in another Td, means at t=” Clk_Period + Td + T_launch”.
• This second set of data is going to update/override the first set of data present at FF2.
• As per the Hold Definition, data should be stable till “T_hold” (Hold time of FF2) time after the Clock edge (which is at t= “Clk_Period + T_capture”).
• Means Next set of data should not reach FF2 before t= “Clk_Period + T_capture + T_hold”
So For NO HOLD VIOLATION:

=> Clk_Period + Td + T_launch >  Clk_Period + T_capture + T_hold
=> Td >  (T_capture -  T_launch ) + T_hold

Summary of this post:

Clock Period Condition:
Clock period > Setup time + Hold Time

Max Delay/ Setup Condition:
Td < Clk_Period + (T_capture - T_launch) – T_setup

Min Delay / Hold Condition:
Td >  (T_capture -  T_launch ) + T_hold

In the next part we will discuss
• More examples which will explain the above conditions in more details.
• How to fix the Setup and hold violation, if we can neither decrease nor increase the Delay in the Data path?

1. Awesome :) crystal clear..

2. Thanks alot for all of your posts...eagerly waiting for your next post...:) Also read your posts on design constraints...simply great!!!.....waiting for your next post in that series as well.......being greedy...:)

1. thanks for appreciation. I would request you to drop a mail on our mail id Or Like Facebook page - so that you can get regular updates from us.

3. Just Awesome like previous :)

4. Thank you for the article. Helping me in my transition into VLSI from college. Hare Krishna ! ( Thanks to the creator who has given you such abilities )

5. Thanks Sir.
Whole blog about STA was so helpul

6. Excellently explained! Thank you so much

7. chokran sir

9. great work sir.But what happens if there is a cascaded structure of flops ?? single buffer insertion may delay the other flops in getting its input ??

1. Hi abubacker,

Analyse the circuit and if the delay isn't required to be passed on to the next flop stage then introduce the delay(insert_buffer) just before the required flop's clk pin i,e make sure the path is not common or shared to any other line. Hope this clears your doubt.

10. How do you constrain a clock enable signal against the edge of the clock?
Clock enable pulses used in multy-cycle path have routing delays, so they have alsotiming specifications.

11. Excellent!!