## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Process Variation Other Topic

## Thursday, April 7, 2011

### "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a)

 Part1 Part2 Part3a Part3b Part3c Part4a Part4b Part4c Part5a Part 8

Static Timing analysis is divided into several parts:

Its been long time, people are asking about Setup and Hold time blog. Finally time come for that. :)

The way we will discuss this concept in the following manner
1. What is SetUp and Hold time?
2. Definition of Setup and Hold.
3. Setup and Hold Violation.
4. How to calculate the Setup and Hold violation in a design?
I saw that lots of people are confused with respect to this concept. And the reason of this are
1. They know the definition but don't know the origin or say concept behind Setup and Hold timing.
2. They know the formula for calculating setup and hold violation but don't know how this formula come in picture.
3. They become confuse by few of the terminology like capture path delay, launch path delay, previous clock cycle, current clock cycle, data path delay, slew, setup slew, hold slew, min and max concept, slowest path and fastest path, min and max corner, best and worst case etc during the explanation of Setup and Hold Timings/Violation.
I hope I can clarify your confusion. Let me explain this and if you face any problem let me know.

What is Setup and Hold time?

To understand the origin of the Setup and Hold time concepts first understand it with respect to a System as shown in the fig. An Input DIN and external clock CLK are buffered and passes through combinational logic before they reach a synchronous input and a clock input of a D flipflop (positive edge triggered). Now to capture the data correctly at D flip flop, data should be present at the time of positive edge of clock signal at the C pin ( to know the detail just read basis of D flipflop).
Note: here we are assuming D flip flop is ideal so Zero hold and setup time for this.
﻿﻿
 SetUp and Hold Time of a System
﻿﻿
There may be only 2 condition.
• Tpd DIN > Tpd Clk
• For capture the data at the same time when Clock signal (positive clock edge) reaches at pin C, you have to apply the input Data at pin DIN "Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK.
• In other word, at DIN pin, Data should be stable "Ts(in)" time before the positive clock edge at CLK pin.
• This Time "Ts(in)" is know as Setup time of the System.
• Tpd DIN < Tpd Clk
• For capture the data at the same time when clock signal (positive clock edge) reaches at pin C, input Data at pin DIN should not change before "Th(in)= (Tpd Clk) - (Tpd DIN)" time. If it will change, positive clock edge at pin C will capture the next data.
• In other word, at DIN pin, Data should be stable "Th(in)" time after the positive clock edge at CLK pin.
• This time "Th(in)" is know as Hold Time of the System.
From the above condition it looks like that both the condition can't exist at the same time and you are right. But we have to consider few more things in this.
• Worst case and best case (Max delay and min delay)
• Because of environment condition or because of PVT, we can do this analysis for the worst case ( max delay) and best case ( min delay) also.
• Shortest Path or Longest path ( Min Delay and Max delay)
• If combinational logic has multiple paths, the we have to do this analysis for the shortest path ( min delay) and longest path ( max delay) also.
So we can say that above condition can be like this.
• Tpd DIN (max) > Tpd Clk (min)
• SetUp time == Tpd DIN (max) - Tpd Clk (min)
• Tpd DIN (min) < Tpd Clk (max)
• Hold time == Tpd Clk (max) - Tpd DIN (min)
For example for combinational logic delays are
Data path (max, min) = (5ns, 4 ns)
Clock path (max, min) = (4.5ns, 4.1ns)
Then Setup time= 5-4.1=0.9ns
Hold time is = 4.5-4=0.5ns

Now similar type of explanation we can give for a D flip flop.  There is a combinational logic between C and Q , between D and Q of the Flipflop. There are different delays in those conbinational logic and based on there max and min value , a flipflop has Setup and Hold time. One circuitry of the positive edge triggered D flip is shown below.
 Positive Edge Triggered D flip-flop

There are different ways for making the D flip flop. Like by JK flipflop, master slave flipflop, Using 2 D type latches etc. Since the internal circuitry is different for each type of Flipflop, the Setup and Hold time is different for every Flipflop.

Definition:
Setup Time:
• Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop.
• Or In short I can say that the amount of time the Synchronous input (D) must be stable before the active edge of the Clock.
• The Time when input data is available and stable before the clock pulse is applied is called Setup time.
Hold time:
• Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.
• Or in short I can say that the amount of time the synchronous input (D) must be stable after the active edge of clock.
• The Time after clock pulse where data input is held stable is called hold time.

Setup and Hold Violation:

In simple language-
If Setup time is Ts for a flip-flop and if data is not stable before Ts time from active edge of the clock, there is a Setup violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) before active clock edge, then it's a Setup violation.
And If hold time is Th for a flip flop and if data is not stable after Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.

How to calculate the setup and hold violation in a design.. please see the next blog.

1. this is really useful... thank you very much...
Really looking forward for your future posts...

2. Thanks for such comments. I will update you once there will be any new post. you can also subscribe to my blog or by twitter account to get a regular update.

3. Nice explanation with useful examples. Thanks!!

5. Thanks man ur work cleared most of my concepts....

6. it was like drinking water in the middle of the desert. so satisfying

7. one of the nice compliment I ever get.

thanks man

8. what is meaning of negative propagation delay ?
and how to obtain it?

9. Hey.. This blog is awesome. I was very confused with setup and hold time. I had to attend NVIDIA interview. Very happy tat i got to know this blog at the right time. I was able to answer qns on setup and hold time violations. And i got selected.. Thanks a lotttttttttttt :)

1. hi naveen,

congrts for ur selection...can you tell me wat type of questions do they ask in interview and written and how shud i prepare for that??....

10. Hi Naveen,
Thanks for compliment.. and congrats for NVIDIA selection. i am happy for you.

Hi Anonymous- with respect to negative propagation delay.. I am going to post it in FAQ section. You will find that soon. Drop a mail to my mail id ... I will let you know as soon as I post their.

1. hi.. even i too have the same doubt about -ve propagation delay..
send me also..

voonnasandeep@gmail.com

11. Not a single textbook out there explains these things in such an easy to understand manner !!

Brilliant work :)

12. jbhjbbhjuh

13. Hi when a Setup or Hold time violation happens the flip flop enters into metastable state and the output will be unpredictable. But there is a statement in the section 'Tpd DIN < Tpd CLK' saying that the if there is a hold time violation the next data will be sampled. Isn't the unpredictability of the output in the metastable state the main problem?

1. Hey AVI that is the actual problem with the hold violation. Both the ways it is true next data will be sampled and data is unpredictable. during one clock period only one data should be captured and you are expecting the data that is just launched in the previous stage. But due to hold time violation that is data arriving very quickly the data that should be captured in the next clock will be captured in the present clock and you are unaware of the data that is captured and you cannot how that will modify your circuit functionality.

14. Thanks for sharing your info. I really appreciate your efforts and I will be waiting for your further write ups thanks once again.
Vee Eee Technologies

15. u r just great..............helpful blog,want to get more like this.........good job

16. Thanks for sharing your info. I really appreciate your efforts and I will be waiting for your further write ups thanks once again.

17. THANKS for sharing your information..!

18. hi there,
your article on setup and hold time is superb ,finally reached here after searching over the net

19. thanks all for appreciating my work.

20. Great work... crystal clear..

21. admin , i reaaly vey thankful to u.......i am trying to larn this all the stuffs from past 1 months but got cleared after reading ur blog....u r d best...keep adding more ...also add some more examples on how to find max freq of clock in STA....thanks again!

22. very nice thanks for sharing

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Type “Let It Snow” on @Google If you click and drag you can wipe the snow away. It is great. source: http://le-titsnow.blogspot.com

23. i feel very happy to get d concept very clearly. thanks to u for spending time in sharing all this. u r doing a great job especially for students like me...thank u so much::)

24. God cudnt be everywer to clear doubts so created experts like you!

sir,so simple and so clear explanation.
ultimate destination for timing analysis.

25. 1 doubt, wat hapns if
Tpd DIN = Tpd Clk?

it was askd in d interview.
vil it be setup time or hold time vilolation?!

1. Hi Siv,

Its there in the blog itself.
See for setup following condition should met..
Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
for hold following

Now if TpdDIN = Tpd Clk -- Means data is not getting proper time to get stable before clock -- so this is the case of Setup Violation for sure.

for hold data should be stable after that (clock pulse)... and data can change only when next data will come (just to replace the previous one).. so if for every data stream Tpd DIN == Tpd CLK -- then data remain stable for 1 clock pulse in general. And there should not be any hold violation.

I hope you get my point.

2. In my opinion, if TpdDin = TpdClk Din signal should meet Ts and Th times of internal FF. So as we have ideal FF here Din and Clk can go simultaneously without violation.

Please correct me if i'm wrong.

26. vil ther be set up and hold time for latches?
as both input(D and clk pass thru same gates, unlike diff gates in FF)

1. there are .. please check the basic knowledge from the previous part of this series.
Sometime later I will post a blog for setup and hold analysis for latches also.

2. thanq u so much
i AM so curious to know MORE about u, plz tell, r u IIT PROFESSOR?

27. Sir, i Got job in LSI LOGIC, SOC design engineer.
Thank you so much for your blog. I wanted to know more about u plz.

1. Hi,

First of all, congrats to you. What exactly you wanted to know about me? Please drop me a mail on my mail id.

28. koppad and siv , both are me only.

29. Thanks a lot sir.i read so many ebooks pdfs but nothing has given me this much clarity.can you please explain with different problems so that it will be easy for me to attend for an interview

1. I will try .. in the mean time please read next 2 parts.. there you will get a lot of other example.

30. sir,
does your blog contains info regarding VERILOG and SYSTEM VERILOG also???i am working for a company fron past 1 year .I have done only one project in vhdl.Now layoff started in my compny.I want to shift.So can please guide me

1. Hi Rishitha,

Right Now, there is no info regarding Verilog in my blog. There are plan for doing this .. but not in near future. But you can find a lot of info on other blogs/website.

31. This comment has been removed by the author.

Your Blog is very useful to me......,I am a fresher 2011 pass out searching for job in Backend(Vlsi physical design).I have taken training in Vlsi Physical Design for Eight months if their are any fresher openings you please post in this blog or mail me at raviteja.vlsi@hotmail.com......,Really this blog is very useful to me....,Before knowing this blog i was little confused with setup and hold time calculations but now it is clarified...., Thank You Very Much.....,

D.Raviteja

1. Hi Ravi,
Its very difficult to trace the opining for fresher/experienced people in the VLSI domain right now. So I can't promise you regarding this. But there are several other sites where you can check and apply also.

33. thanks a lot.. this was a very useful article and really cleared away confusions

34. Hi,
I am not able to clearly understand the explaination given for What is Setup time. Can you please explain more in detail by giving numbers along with waveforms for Tpd DIN and Tpd CLK.For example::
1) Let us take Tpd DIN = 7ps and Tpd CLK = 4ps and let us say a positive edge occurs at pin CLK at 2ps. So the clock will reach at "C" pin of the flop at 6ps, then as per the explaination we have to apply data at DPIN at 1 ps (7-6) before the positive edge which occurs at pin CLK which occurse at 2 ps. But the data will be captured at 2ps and as Tpd DIN is 7ps it will reach D pin of the flop at 9ps.
So the data is not present at D pin of the flop at 6ps
2) Let us take only Tpd DIN = 7ps and Tpd = 6ps
>>>apply the input Data at pin DIN "Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK.
At which time the positive edge will occur so that we can apply the input data.
Please correct if i am wrong.
Thanks

35. hi superb explanation

36. You defined setup and hold time for a system. I want to know how setup and hold time is calculated for a flip flop ?

1. flip-flop is also a system.. you can see that I have applied the same concept for D type of flipflop.

37. Hi ,
I am a bit confused about the minimum and maximum conditions used for the below conditions.
Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

Kindly help to elucidate the reason for the selection of min and max values for the setup and hold times.

38. This blog is simply mind blowing...all compact and easy to understand sections...thanx a lot dude..!!

39. Thanks for your explanation. Before your notes, I was in a state of lack of clarity of setup and hold time, I know their definitions but I was unable to apply them to the circuits. Now I got the clarity. I have a doubt. Why people always hide things of their knowledge. They always confuse us by saying definitions. They never say any thing clearly like u. Thank you one more time. I hope u should continue this block for us.

40. This comment has been removed by the author.

41. Hi Thanks for the concepts you have explained. It is awesome !!! I had an interview question like this: Which is more important - Set up time or hold time?

1. Can you give me an answer for that?
What happens to the system if the clock frequency is reduced?

2. Hi,

Please refer 6a,6b and 6c and also 5a and 5b. I am sure you will get the ans.
See I can ans here .. but my intension is that u should figure out your own with the help of basics. :)
Still u didn't get the ans.. ping me again.

42. HI There is a mistake there .. corrected below

And If hold time is Th for a flip flop and if data is not stable ***** Before ***** Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.

43. This doesn't look right?
Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

It needs to other way round?
SetUp time == Tpd Clk (min) - Tpd DIN (max)

44. Finally i got what exactley setup and hold time .Thanks a lott Sir

45. Thanks a lot for the blog itz very needfull especially for beginners. Each and every concept explained in depth with different examples.

46. Thanks very much,this stuff is very good for setup and hold time concept

48. Blogs like vlsi-expert, digitalelectronics, etc. are all owned and updated by Indians. You guys make us all so very proud!

This blog is simply incredible!!!

49. Hi! I must congratulate you for this wonderful blog that you've been maintaining, and must say that it's been of much help.

However, I find one thing confusing here.

I think the Setup and Hold time equations should be:
T(set-up)[max] = T(clock)[min] - T(data)[max]
T(hold)[max] = T(data)[min] - T(clock)[max]

The only difference between what I think and what's present in the above article is the sign of the result, but even that is quite significant!

In my equation, when the min. Clock time is larger than the max. Data time, we get a +ve Set-up time, like should usually be. Your equation, though yields a +ve Set-up time when the max. Data time is larger than the min. Clock time, which instead looks like Set-up violation!

I will be extremely grateful to you if you could clarify this point to me and remove my confusion. I might have missed some point here. I'm sure many others must have had this doubt, so your reply to this comment could benefit many, including me!

Thanks again, for your wonderful blog!

1. I think I've got the point here! Oh yes, I think I have!
The equation you've posted here is to calculate these times, and not validate. Yep, I've cracked it!! :)

I will still await your valuable comment here. Intezaar rahegaa aapke beshkeemati tippanee kaa! :)

2. I think .. No need for any specific comment. You got the right thing at the right time.

3. i dont understand the equations below can you please elaborate?
Tpd DIN (max) > Tpd Clk (min)
SetUp time == Tpd DIN (max) - Tpd Clk (min)
Tpd DIN (min) < Tpd Clk (max)
Hold time == Tpd Clk (max) - Tpd DIN (min)

i understand this equation
T(set-up)[max] = T(clock)[min] - T(data)[max]
T(hold)[max] = T(data)[min] - T(clock)[max]

4. I don't get it. If T clock min is more than T data max, time the clock pulse takes to travel is always more than the time data takes to transfer. That means, clock will always reach after the data is received. So the data should hold it's stability until clock is reached. How can this time be called setup time?
To get a positive setup time from this equation,
T(set-up)[max] = T(clock)[min] - T(data)[max]
is not possible since if clock's min delay is more than data's max delay, it will be a case of Hold time and not setup time. Please correct me where I am wrong.

50. Can you suggest a book for this topic??

51. Dear sir
please that set up time and hold time is for i/p or o/p or both or is set up is for i/p or hold is for o/p