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Friday, January 10, 2014

10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8)

10 Ways to fix SETUP and HOLD violation:

Till now, We have discussed basic concepts of fixing the Setup and Hold violation which include 
  • Different formulas + explanation to identify the type of violation in design.
  • How to fix those violations?
  • Different methods of Increasing and Decreasing the Delay in the circuit to fix these type of violations?
And Now it’s the time to list down different methods to fix these violations. I have also explained in brief each and every method, which also referring previous post for reference. One point to remember here that Fixing the Setup and Hold Violation are reverse in nature. All the methods which are applicable to fix one type of methods , hold true and can be apply to fix other type of if we will do the opposite thing. E.g - if setup can be fix by adding 1 buffer in some path then Hold can be fix by removing buffer in that path. (You will see these things below in the post)

In the last you will also find DOs and DON'Ts and recommended approach to fix these violations. These Recommendations helps designer in reducing iteration and fix the violations fast. 

8 Ways To Fix Setup violation:

Setup violations are essentially where the data path is too slow compared to the clock speed at the capture flip-flop. With that in mind there are several things a designer can do to fix the setup violations.

Method 1Reduce the amount of buffering in the path.
  • It will reduce the cell delay but increase the wire delay. So if we can reduce more cell delay in comparison to wire delay, the effective stage delay decreases.

Method 2 : Replace buffers with 2 Inverters place farther apart
  • Adding 2 inverters in place of 1 buffer, reducing the overall stage delay.
    • Adding inverter decreases the transition time 2 times then the existing buffer gate. Due to that, the RC delay of the wire (interconnect delay) decreases.
    • As such cell delay of 1 buffer gate ≈ cell delay of 2 Inverter gate
    • So stage delay (cell delay + wire delay) in case of single buffer < stage delay in case of 2 inverter in the same path.
    • You will get the clear understanding by following figure and you can refer the first post to understand how transition time varies across the wire.

Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.
  • Low Vt decrease the transition time and so propagation delay decreases.
  • HVT/NVT/LVT type cells have same size and pin position. In both leakage current and speed, LVT>NVT>HVT. So replace HVT with NVT or LVT will speed up the timing without disturb layout.
  • Negative effect: Leakage current/power also increases.

Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)
  • Explained the basic and details in the previous post
  • Note: Normally larger cell has higher speed. But some special cell may have larger cell slower than normal cell. Check the technology library timing table to find out these special cells. Increasing driver is very commonly used in setup fix.
  • Negative effect: Higher power consumption and more area used in the layout.
  • I have notice one explanation in book <book name>. I am copying and pasting (not 100%) that here because I like that one. J Marked the important part by Bold.
    • The basic layout technique for reducing the gate delay consists in connecting MOS devices in parallel.
    • The equivalent width of the resulting MOS device is the sum of each elementary gate width. Both nMOS and pMOS devices are designed using parallel elementary devices.
    • Most cell libraries include so-called x1, x2, x4, x8 inverters.
    • The x1 inverter has the minimum size, and is targeted for low speed, low power operations.
    • The x2 inverter uses two devices x1 inverters, in parallel. The resulting circuit is an inverter with twice the current capabilities. The output capacitance may be charge and discharged twice as fast as for the basic inverter (see below figure), because the Ron resistance of the MOS device is divided by two. The price to pay is a higher power consumption.
    • The equivalent Ron resistance of the x4 inverter is divided by four.
    • The clock signals, bus, ports and long wires with severe time constraints use such high drive circuits.

Method 5 : Insert Buffers
  • Some time we insert the buffer to decrease over all delay in case of log wire.
  • Inserting buffer decreases the transition time, which decreases the wire delay.
  • If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all delay decreases.
  • Negative Effect: Area will increase and increase in the power consumption.

Method 6 : Inserting repeaters:
  • Concepts of Repeaters are same as I have discussed in “Inserting the Buffer” (above point). Just I am trying to explain this in a different way but the over concept are same.
  • Long distance routing means a huge RC loading due to a series of RC delays, as shown in figure. A good alternative is to use repeaters, by splitting the line into several pieces. Why can this solution be better in terms of delay? Because the gate delay is quite small compared to the RC delay.

  • In case of Interconnect driven by a single inverter, the propagation delay become
    • Tdelay= tgate+ nR.nC = tgate + n­2RC
  • If two repeaters are inserted, the delay becomes:
    • Tdelay=tgate (delay of inverter) + 2tgate (delay of repeater) +3RC = 3tgate + 3RC
  • So you can see how RC delay is impacting in case of non-repeater in the circuit.
  • Consequently, if the gate delay is much smaller than the RC delay, repeaters improve the switching speed performances, at the price of higher power consumption.
  • Below figure helps you to understand the practical use of this.

Method 7 : Adjust cell position in layout.
  • Let’s assume there are 2 gate (GATE A and GATE B) separated by 1000um. There is another GATE C placed at the distance of 900um from GATE A.
  • If we re-position the GATE C at 500um from GATE A (center of GATE A and B), overall delay between GATE A and B decreases.
  • You will get the clear understanding by first post and the following diagram.
  • Note: The placement in layout may prevent such movement. Always use layout viewer to check if there are any spare space to move the critical cell to an optimal location.

Method 8 : Clock skew:
  • By delaying the clock to the end point can relax the timing of the path, but you have to make sure the downstream paths are not critical paths.
  • Related to clock skew basic – I will discuss that in SI section.

2 Ways to Fix Hold Violations:

Hold violation is the opposite of setup violation. Hold violation happen when data is too fast compared to the clock speed. For fixing the hold violation, delay should be increases in the data path.
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be reduced.
The designer needs to simply add more delay to the data path. This can be done by

Method 9 : By Adding delays.
  • Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold violation.
  • Note: The hold violation path may have its start point or end point in other setup violation paths. So we have to take extra care before adding the buffer/delay.
    • E.G. if the endpoint of hold violation path has setup violation with respect to some other path, insert the buffer/delay nearer to start point of hold violation path. Else the setup violation increases in other path.
    • if the start point of hold violation path has setup violation with respect to some other path, insert the buffer/delay nearer to end point of hold violation path. Else the setup violation increases in other path.
  • I am sure you may be asking what is this and why?
  • Below figure and explanation can help you to understand this.
  • From below figure, you can also conclude that don’t add buffer/delay in the common segment of 2 paths (where one path has hold violation and other setup violation).

Method 10 : Decreasing the size of certain cells in the data path.
  • It is better to reduce the cells closer to the capture flip flop because there is less likely hood of affecting other paths and causing new errors.

Note: Following points are recommended while fixing setup and hold violations.
  • Make modification to the data path only.
    • Adjusting register location or removing/adding buffers to the clock path will fix the violation that but it may cause more violations for some other paths which may not present before.
  • First try to fix setup violation as much as possible. Then later on start fixing hold violation.
  • In general, hold time will be fixed during back-end work (during PNR) while building clock tree. If u r a front-end designer, concentrate on fixing setup time violations rather than hold violations.
  • Fix all the hold violation, if you have to choose between setup and hold.
    • If a chip is done with some setup violations it can work by reducing the frequency.
    • If a chip is done with hold violations, we have “JUST DUMP” the chip. 


  1. Awesome Learning Experience. It is a very interesting blog to refresh the concepts on STA. Thank you:)

  2. Kudos to you!! This is one great blog for learners like me! Thank you loads for all your effort! May god bless you!

  3. really nice to learn...

  4. Explanation in awesome. Efficient use of examples. Looking forward to read more topics.

  5. thank you very much.

  6. The explanation is great. Thanks for sharing the post :)

  7. Thank you very informative :)

  8. Hi, Sir,

    when will RC delay (wire delay) > cell delay?


  9. Thank you for a very informative blog on STA. Lot of concepts got clearer.

  10. Very nice and great work sir..Kudos to you..

  11. Great stuff. Check method 2, bullet 3.

  12. If a chip has hold violations it can be fixed by changing the supply voltage. For hold you might need to increase the logic delay and so decreasing the supply voltage. This might actually trigger set up violation but care needs to be taken.

  13. This was really helpful. Can you please suggest any sources to practice questions on this topic?

  14. Thank you very much

  15. wow super pakka very good explanation

  16. Thanks a lot!!! learnt a lot from this blog

  17. Hi,
    You have said, "hold violation happens when data is too fast compared to clock speed". But how can hold violation be related to clock speed? Here with clock speed do you mean delay in capture path or clock frequency?

  18. You got to efficiently explain what Synopsys and Cadence manuals don't do. Thanks a mill.

  19. Who fix these setup and hold violation?
    Whether the designer or backend team?

    1. Before I can help you with the Answer - you have to differentiate the work of Designer and backend Team? What do you mean by Backend team ?

  20. sir ur saying like first go for setup violation then after for hold ..but after CTS also preference only for setup first and then for hold ???...plz clearify

  21. Thanks for the blog post . Quick query : Hold time of a flop dictates that logic delay of the combinational path be more than a given value ( Tdelay > Thold ) . So can we say that Thold puts a limit on the max frequency of operation since 1/ (max freq) > Tsetup + Tdelay ( I am ignoring c2q delays and clk skews for simplicity )

    1. I can reply you .. but best is you check these 2 Articles

      At the end of these 2, I am sure you can yourself figure out whether it has dependency or not. If Not - Ping me again - I will explain you.

    2. Hi, thanks for the reply.. I read through the blogs; still I think there is a dependence ie If I reduce the combinational path delay to a very low value (~0) then there would be hold violation; hence "max freq period" = Tsetup + Tcombdelay.

  22. Thanks a lot for information...............

  23. If there is a long wire between cells then adding buffers will reduces the delay through decrease in transition time. So, my question is, how is optimum number of buffers are determined? I hope adding in more numbers will increase delay than reducing it!!

    1. You are right .. If you will add more buffer , it will increase the delay. There are lot of ways to find the optimum number of buffers. Basically there are algorithm for that. but this post is just to provide a insight about the methods which can help you in the field or during design.
      Other Algorithm I will try to cover in some other post.

  24. Is it possible to fix the hold violation of a manufactured chip by tweaking operating condition, e.g., decreasing supply voltage or increasing temperature?

  25. Hi,

    I am using Vivado design suite from Xilinx. After synthesis, in timing summary, I got a some setup time violations. There was an option to maximize the delay from start point to end point. After following that step, the setup time violation issue was solved.

    The above condition contradicts the fact that "decreasing the delay" fixes the setup time violation. Please explain.

  26. hi expert
    what about pipeline technique?
    if the timing is not meeting b/wn two flops by regular methods .we can insert flop to meet timing is it correct or not? please reply me

  27. So stage delay (cell delay + wire delay) in case of single buffer < stage delay in case of 2 inverter in the same path. I think here stage delay of buffer is > stage delay of 2inverters...also can you please explain why transition time of inverter is low..thank you

  28. wat is the relation between violations and crosstalk.and also how do v relate delay with crosstalk

  29. Can we Change the setup and hold violations after the chip is manufactured?


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