STA & SI:: Chapter 2: Static Timing Analysis | |||||

2.1 | 2.2 | 2.3a | 2.3b | 2.3c | 2.4a |

Timing Paths | Time Borrowing | Basic Concept Of Setup-Hold | Basic Concept of Setup-Hold Violation | Examples:S-H Time/Violation | Timing Path Delay |

2.4b | 2.4c | 2.5a | 2.5b | 2.6a | 2.6b |

Interconnect Delay Models | Delay - Wire Load Model | Maximum Clock Frequency | Calculate “Max Clock Freq”-Examples | Fix Setup-Hold Violation-1 | Fix Setup-Hold Violation-2 |

2.6c | 2.7a | 2.7b | 2.7c | 2.8 | |

Fix Setup-Hold Violation-3 | Incr/Decr Delay Method-1 | Incr/Decr Delay Method-2 | Incr/Decr Delay Method-3 | 10 ways to fix Setup-Hold Violation. |

Static Timing analysis is divided into several parts:

- Part1 -> Timing Paths
- Part2 -> Time Borrowing
- Part3a -> Basic Concept Of Setup and Hold
- Part3b -> Basic Concept of Setup and Hold Violation
- Part3c -> Practical Examples for Setup and Hold Time / Violation
- Part4a -> Delay - Timing Path Delay
- Part4b -> Delay - Interconnect Delay Models
- Part4c -> Delay - Wire Load Model
- Part5a -> Maximum Clock Frequency
- Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
- Part 6a -> How to solve Setup and Hold Violation (basic example)
- Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
- Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
- Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
- Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
- Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
- Part 8 -> 10 ways to fix Setup and Hold Violation.

**Now the question is: What is Wire Load Models (WLM).**

Wire loading models

- Used to estimate the interconnect wire delay during pre-layout in a design cycle.
- Wire load information is based on statistics from physical layout parasitic
- Information from the statistics is used in both conservative and aggressive tables.
- The conservative tables are based on “mean value” plus 3-sigma; the aggressive tables on “mean value” plus 1-sigma.
- Different for different technology.
- Wire load models are approximated from one technology to another based on scaling factors. Due to these approximations, the accuracy of these models diminish over multiple technology nodes
- Describes effect of wire length and fanout on
- Resistance
- Capacitance
- Area of the nets.
- All attributes (R, C and Area) are given per unit length wire.
- Slope value is used to characterize linear fanout.
- Basically a set of tables
- Net fanout vs load
- Net fanout vs resistance
- Net fanout vs area

One example of such type of table is:

Net Fanout | Resistance KΩ | Capacitance pF |

1 | 0.00498 | 0.00312 |

2 | 0.01295 | 0.00812 |

3 | 0.02092 | 0.01312 |

4 | 0.02888 | 0.01811 |

As per this

The following are few snapshot of the different format of wire load model.

wire_load("WLM1") {

resistance : 0.0006 ;------>R per unit length

capacitance : 0.0001 ;------> C per unit length

area : 0.1 ;------> Area per unit length

slope : 1.5 ;------> Used for linear extrapolation

fanout_length(1, 0.002) ; ------> at fanout “1” length of the wire is 0.002

fanout_length(2, 0.006);

fanout_length(3, 0.009);

fanout_length(4, 0.015);

fanout_length(5, 0.020);

fanout_length(7, 0.028); ------> at fanout “7” length of the wire is 0.028

fanout_length(8, 0.030);

fanout_length(9, 0.035);

fanout_length(10, 0.040);

}

wire_load("WLM2") {

fanout_length( 1, 1 );

fanout_length( 2, 2 );

fanout_capacitance( 1, 0.002 );

fanout_capacitance( 2, 0.004 );

fanout_capacitance( 3, 0.006 );

fanout_capacitance( 4, 0.008 );

fanout_capacitance( 5, 0.010 );

fanout_capacitance( 6, 0.013 );

fanout_capacitance( 7, 0.015 );

fanout_capacitance( 8, 0.019 );

fanout_capacitance( 9, 0.023 );

fanout_capacitance( 10, 0.027);

fanout_resistance( 1, 0.01 );

fanout_resistance( 2, 0.015 );

fanout_resistance( 3, 0.022 );

fanout_resistance( 4, 0.026 );

fanout_resistance( 5, 0.030 );

fanout_resistance( 6, 0.035 );

fanout_resistance( 7, 0.039 );

fanout_resistance( 8, 0.048 );

fanout_resistance( 9, 0.057 );

fanout_resistance( 10, 0.06 );

fanout_area( 1, 0.11 );

fanout_area( 20, 2.20 );

}

Here --

Area, Resistance and Capacitance are in per unit length of the interconnect.

The slope is the extrapolation slop to be used for data points that are not specified in the fan-out length table.

In general, not all fanouts are mentioned in a given WLM lookup table. For example, in above WLM1 and WLM2 lookup table, capacitance and resistance values for fanouts 1, 2, 3, 4, 5, 7, 8, 9, 10 is given. If we want to estimate the values at fanouts in the gaps (e.g. from 6) or outside the fanout range specified in the table (e.g Fanout 20), we have to calculated those value using (linear) interpolation and extrapolation.

__For WLM1__**For Fanout=20**

Since its more than the max value of Fanout available in table (i.e 10) , so we have to perform extrapolation.

*Net length = <length of net at fanout 10> + (20-10) x Slope*

*Resistance = <new calculated Net length at fanout 6> x Resistance or Capacitance value per unit length*

*Capacitance = <new calculated Net length at fanout 6> x Capacitance value per unit length*

Net length = 0.040 + 10 x 1.5 (slope) = 15.04 ----------> length of net with fanout of 20

Resistance = 15.04 x 0.0006 = 0.009024 units

Capacitance = 15.04 x 0.0001 = 0.001504 units

**For Fanout=6**

Since it’s between 5 and 7 and corresponding fanout Vs length is available, we can do the interpolation.

*Net length = ( (net length at fanout 5) + (net length at fanout 7) ) / 2*

*Resistance = <new calculated Net length at fanout 20> x Resistance value per unit length*

*Capacitance = <new calculated Net length at fanout 20> x Capacitance value per unit length*

Net length = (0.0020 + 0.0028)/2=0.0048/2=0.0024 ----------> length of net with fanout of 6

Resistance = 0.0024 x 0.0006 = 0.00000144 units

Capacitance = 0.0024 x 0.0001 = 0.00000024 units

In the similar way we can calculate the WLM for any no of fanout value.

WLMs are often used in pre-placement optimization to drive speedups of critical paths. Since timing-driven placement plausibly makes nets on critical paths shorter than average, some optimism may be incorporated into the WLM. Thus, a WLM may actually consist of more than one lookup table, with each table corresponding to a different optimism level. There are several ways to incorporate the optimism level. If we use the WLMs that come from the (ASIC vendor’s) design library, usually there are several tables from which we can select. We can also increase the optimism level of a WLM by multiplying all values in the WLM by some factor less than 1.2 For example, we can use 0.25, 0.5, or 0.75.

WLM Types

For flows that run timing-based logic optimization before placement, there are three basic types of WLMs that can be used:

- Statistical WLMs
- Are based on averages over many similar designs using the same or similar physical libraries.
- Structural WLMs
- Use information about neighboring nets, rather than just fanout and module size information.
- Custom WLMs
- Are based on the current design after placement and routing, but before the current iteration of preplacement synthesis.

**Now the Question is: Where do the wire load models come from?**

Normally the semiconductor vendors will develop the models.

ASIC vendors typically develop wireload models based on statistical information taken from a variety of example designs. For all the nets with a particular fanout, the number of nets with a given capacitance is plotted as a histogram. A single capacitance value is picked to represent this fanout value in the wireload model. If a very conservative wireload model is desired, the 90% decile might be picked (i.e. 90% of the nets in the sample have a capacitance smaller than that value).

In this example 90% of nets have a capacitance smaller then 0.198pf. So in the WLM table, you will notice that fanout_capacitance( 3, 0.198 ).

Similar statistics are gathered for resistance and net area.

Usually the vendor supplies a family of wireload models, each to be used for a different size design. This is called

*area-based wireload selection*

__Few Advance concepts:__Till now we have discussed that for a particular Net you can estimate the RC value as per the WLM. Let me ask you one question. What if your design is hierarchical? Do you think even in that case you can use the same WLM for a particular net which is crossing the hierarchical boundaries? Short ANS is: you can use it but you will lose the accuracy.

Just to solve this problem, Vendors usually supplies multiple WLMs. There are different Modes for WLM analysis- few important are:

WLM analysis has three modes:

- Top:
- Consider the design as it has no hierocracy and use the WLM for the top module to calculate delays for all modules.
- Any low level WLM is ignored.
- Enclosed:
- Use the WLM of the module which completely encloses the net to compute delay for that net.
- Segmented:
- If a net goes across several WLM, use the WLM that corresponds to that portion of the net which it encloses only.

Good Basic information.

ReplyDeletegood work

ReplyDeletenice info.

ReplyDeleteExcellent explanation so far. very effective.

ReplyDeleteThanks a lot...

Waiting for the next one.

How does one calculate RC delay between two cells given only placement information without routing?

ReplyDeleteHI, Simple ans of this question is ...

DeleteWire load models are approximated from one technology to another based on scaling factors. Means if you are in the cycle of 28nm, then you can use your experience of 32nm and scale it for 28nm.

So one thing important here-- these are not accurate value -- these are always approximate. its like you never traveled from London to Newyork... but still you have idea about the time you will take ... if you fly/drive/walk. :)

1) Why Area information is enclosed in WLM? When does it become useful?

ReplyDelete2) As for the transition delay over the cell, could it calculated using WLM? How?

This comment has been removed by the author.

Deleteexcellent work

ReplyDeletebut i had a question:

what do you mean by the fan-out here?? .... you didn't mean the fan-out of the driver or am i wrong??

This comment has been removed by the author.

ReplyDeleteIs that a mistake in WLM calculation?

ReplyDeleteThe formula for capacitance and resistance of fanout = 20 should be

resistance = (new calculated net length for fanout 20) x resistance value of unit length

capacitance = (new calculated net length for fanout 20) x capacitance value of unit length

And for fanout = 6, they should be

resistance = (new calculated net length for fanout 6) x resistance value of unit length

capacitance = (new calculated net length for fanout 6) x capacitance value of unit length

Their order should be reversed.

good one. thanks

ReplyDeletesuppose length of the routing is L and if we insert a buffer in the middle, what happens to the total delay?

ReplyDeleteyou have to pick different value of Length from the wire load model table.

DeleteI clicked to your website and it’s quite interesting. I see so many things that I haven’t known before. Thank you for submitted your website.

ReplyDeleteSeeing the trend in the WLM, length of the wire increases with the fan-out. What is the logical reasoning behind this ?

ReplyDeleteThanks

Seeing the trend in the WLM, length of the wire increases with the fan-out. What is the logical reasoning behind this ?

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