Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

Tuesday, May 3, 2011

"Examples Of Setup and Hold time" : Static Timing Analysis (STA) basic (Part 3c)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.
Static Timing analysis is divided into several parts:

Till now we have discussed a lot of theory about setup and hold time (with and without Example). Now it’s time to discuss the practical implementation of that. Means in a circuit
• How will you calculate the setup and hold values?
• How will you analyze setup and hold violation in a circuit?
• If you have to improve timing of a circuit then what can you do?
There are few formulas to calculate different parameter ( Theory of those I already explained in my previous blogs). I am not going to explain those right now. First we will solve few examples which will give you an basic idea about these formulas, then in the last I will summarize all those in one place.

I saw a lot of confusion with respect to setup and hold timing calculation. Actually there are two things.
• Timing Specification of a Block/Circuit/Library:
• You have a block with input A and output Y. Some combinational logic is there between A and Y. Now you have to calculate following parameters for that block
• Setup Time Value at input A
• Hold Time value at input A.
• Maximum operating Clock Frequency or Time Period for that block.
• Clock To Y delay value
• Input A to Output Y delay value.
• Timing Violation of a circuit:
• You have to operate a circuit at a particular clock frequency and now you have to find out whether this circuit has any setup or Hold Violation.
So in second case all the parameters are given and you have to find out whether this circuit has any violation or not and In first case you have to find out all the parameters keeping in mind that there should not be any violation.
Lets Discuss in the reverse order.
**********************************************************************************
**********************************************************************************

Problem1: In the following Circuit, Find out whether there is any Setup Or Hold Violation?

Solution:
Hold Analysis:
When a hold check is performed, we have to consider two things-
• Minimum Delay along the data path.
• Maximum Delay along the clock path.
If the difference between the data path and the clock path is negative, then a timing violation has occurred. ( Note: there are few Exceptions for this- We will discuss that some other time)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path
= min(wire delay to the clock input of FF1) + min(Clk-to-Q delay of FF1) +min(cell delay of inverter) + min(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 1+9+6+(1+1)=18ns

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay
= max(wire delay from CLK to Buffer input) + max(cell delay of Buffer) + max(wire delay from Buffer output to FF2/CLK pin) + (hold time of FF2)
=Tclk = 3+9+3+2 = 17 ns

Hold Slack = Td - Tclk = 18ns -17ns = 1ns
Since Hold Slack is positive-> No hold Violation.

Note: If the hold time had been 4 ns instead of 2 ns, then there would have been a hold violation.
Td=18ns and Tclk = 3+9+3+4=19ns
So Hold Slack=Td - Tclk = 18ns - 19ns = -1ns (Violation)

Setup Analysis:
When a setup check is performed, we have to consider two things-
• Maximum Delay along the data path.
• Minimum Delay along the clock path.
If the difference between the clock path and the data path is negative, then a timing violation has occurred. ( Note: there are few Exceptions for this- We will discuss that some other time)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path
= max(wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) +max(cell delay of inverter) + max(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")
=Td = 2+11+9+(2+2) = 26ns

Note: The first part of the clock path delay (during setup calculation) is the clock period, which has been set to 15 ns. Hope You remember in last blog, I have mentioned very clearly that Setup is checked at the next clock cycle. That's the reason for clock path delay we have to include clock period also.

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay
= (Clock period) + min(wire delay from CLK to Buffer input) + min(cell delay of Buffer) + min(wire delay from Buffer output to FF2/CLK pin) - (Setup time of FF2)
=Tclk = 15+2+5+2-4=20ns

Setup Slack = Tclk - Td = 20ns - 26ns = -6ns.
Since Setup Slack is negative -> Setup violation.

Note: A bigger clock period or a less maximum delay of the inverter solve this setup violations in the circuit.
E.g
If Clock period is 22ns then
Tclk = 22+2+5+2-4=31-4=27ns   AND Td = 26ns
Setup Slack = Tclk - Td = 27-26=1ns  (No Violation)

**********************************************************************************
**********************************************************************************

Problem2: In order to work correctly, what should be the Setup and Hold time at Input A in the following Circuit. Also find out the maximum operating frequency for this circuit. (Note: Ignore Wire delay). Where Tsu- Setup time; Thd-Hold Time; Tc2q- Clock-to-Q delay
Solution:
Step1: Find out the maximum Register to register Delay.

Max Register to Register Delay
= (clk-to-Q delay of U2) + (cell delay of U3) + (all wire delay) + (setup time of U1)
= 5 + 8 + 3 = 16 ns.

Note:
• There are 2 register to register paths
• U2 -> U3 ->U1 (Delay=5+8+3=16ns)
• U1 -> U4 -> U2 ( Delay=5+7+3=15ns)
• We have to pick maximum one.

Step2: Find Out Setup Time:

A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns

Note:
• Here we are not using the Clock period. Because we are not suppose to calculate the Setup violation. We are calculating Setup time. Please refer the part3a for the referance.
• All the wire dealy is neglected. If Wire delay present, we have to consider those one.
• There are 2 Data path
• A -> U7 -> U4 -> D of U2 (Data path Delay = 1+7 =8ns )
• A -> U7 -> U3 -> D of U1 ( Data path Delay = 1+8 =9ns )
• Since for Setup calculation we need maximum Data path delay, we have choosen 2nd for our calculation.
Step3: Find Out Hold Time:
A hold time = Hold time of Flipflop + max(Clock path Delay) - min( Data path delay)
=( Hold time of Flipflop + Clk path max delay) - (A2D max delay)
= Thd + Tpd U8 - (Tpd U7 + Tpd U4+wire delay)
= 4 + 2 - (1+7 ) = -2 ns

Note: Same explanation as for Setup time. For hold time we need minimum data path , so we have picked first Data path.

Step4: Find out Clock to Out Time:

Clock to Out
= Cell delay of U8 + Clk-to-Q delay of FlipFlop+ Cell delay of U5+ Cell delay of U6+ (all wire delay)
= Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd
= 2 + 5 + 9 + 6 = 22 ns

Note:
• There are 2 Clock to Out path- one from Flip flop U1 and other from U2.
• Since in this case the Clk-to-Q path for both Flipflop is same, we can consider any path. But in some other Circuit where the delay is different for both the paths, we should consider Max delay path.
Step5: Find Pin to Pine Combinational Delay (A to Y delay)

Pin to Pin Combinational Delay (A to Y)
= U7 Tpd + U5 Tpd + U6 Tpd
= 1 + 9 + 6 = 16 ns

Step5: Find Out Max Clock Frequency:

Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)
= 1/ Max (16, 22, 16)
= 45.5 Mhz

So summery is:

 Parameter Description Min Max Units Tclk Clock Period 22 ns Fclk Clock Frequency 45.5 Mhz Atsu A setup time 10 ns Athd A hold time -2 ns A2Y A to Y Tpd 16 ns Ck2Y Clock to Y tpd 22 ns

Note: Negative hold times are typically specified as 0 ns.

**********************************************************************************
**********************************************************************************

Problem3: In the above Circuit, Try to improve the timing by adding any "buffer" or "Register".

Solution:
Best way of doing this is “Register all Input and Output”. We are adding DFF so same specification (as U2 and U1).

Now follow all those 5 Steps onn by one.
Step1:

Max Register to Register Delay
U2 Tc2q + U5 Tpd + U9 Tsu = 5 + 9 + 3 = 17 ns

Note:
• A lot of Register to Register path
• U8 -> U5 -> U9 (Delay = 5+9+3=17ns)
• U8 -> U4 -> U2 (Delay = 5+7+3=15ns)
• U8 -> U3 -> U1 (Delay = 5+8+3=16ns)
• U1 -> U4 -> U2 (Delay= 5+7+3=15ns)
• U1 -> U5 -> U9 (Delay= 5+9+3=17ns)
• U2 -> U5 -> U9 (Delay = 5+9+3=17ns)
• U2 -> U3 -> U1 (Delay = 5+8+3=16ns)
• Maximum delay is 17ns, Just picked anyone.
Step2:
A setup time = Tsu + A2D Tpd max - Clk Tpd min
= Tsu + (Tpd U7) - Tpd U8
= 3 + (1) - 2 = 2 ns

Note: Only One path between A and D of FF(i.e U8)

Step3:
A hold time = Thd + Clk Tpd max - A2D Tpd min
= Thd + Tpd U8 - (Tpd U7)
= 4 + 2 - ( 1) = 5 ns

Note: Only One path between A and D of FF(i.e U8)

Step4:
Clock to out:
=Tpd U8+ U9 Tc2q  + U6 Tpd
=2+5+6 = 13 ns

Step5:
No direct link between A and Y. So Not Applicable.

Step6:
Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)
= 1/ Max (17, 13)
=58.8 Mhz

 Parameter Description Min Max Units Tclk Clock Period 17 ns Fclk Clock Frequency 58.8 Mhz Atsu A setup time 2 ns Athd A hold time 5 ns Ck2Y Clock to Y tpd 13 ns

**********************************************************************************
**********************************************************************************

I hope This much will help you. Now its the time to summarize all the important things and formulas.

Points to remember:
1. Setup is checked at next clock edge.
2. Hold is checked at same clock edge.
3. For Hold Check ( Checking of hold Violation)
• Minimum Delay along the data path.
• Maximum Delay along the clock path.
4. For SetUp Check ( Checking of Setup Violation)
1. Maximum Delay along the data path.
2. Minimum Delay along the clock path.

 Basic 2 FlipFlop circuit.

Calculation of Setup Violation Check: Consider above circuit of 2 FF connected to each other.

Setup Slack = Required time - Arrival time (since we want data to arrive before it is required)

Where:
Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)
Required time = clock adjust + clock delay FF2 (min) - set up time FF2
Clock adjust = clock period (since setup is analyzed at next edge)

Calculation of Hold Violation Check: Consider above circuit of 2 FF connected to each other.

Hold Slack = Arrival Time - Required time (since we want data to arrive after it is required)

Where:
Arrival time (min) = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)
Required time = clock adjust + clock delay FF2 (max) + hold time FF2
Clock adjust = 0 (since hold is analyzed at same edge)

Calculation of Maximum Clock Frequency:

Max Clock Freq = 1/ Max (Reg2reg delay, Clk2Out delay, Pin2Pin delay)

Where:
Reg2Reg Delay = Clk-to-Q delay of first FF (max) + conb delay (max) + setup time of 2nd FF.
Clk2Out Delay = Clock delay w.r.t FF (max) + clock-to-Q delay of FF1 (max) + comb. delay (max)
Pin2Pin delay = Comb delay between input pin to output pin (max)

1. Thanks... I really appreciate your work.. Nice to see experts like you sharing knowledge in a detailed manner

2. Hi, thanks for such useful blog.
But one comment I wanna say that can you remove all the previous comment (maybe include this), which pointed out the mistake you have been corrected. Its help the audience save much time.
Thanks again for great job!

3. Hi,

Thanks a lot for this blog. Great Job!

4. Hi,

In the 1st problem, for checking hold violation, you calculated hold slack as Td-Tclk, but you mentioned earlier that for calculating hold time we should do Tclk(max)-Td(min), but here I find its opposite, same thing I found in regard to setup time analysis. Can you please clear me that doubt.
By the way, very very nice job. This blog helped me a lot for my interviews. :)
Thanking You

5. Hi,

See there are 2 different things.. ( i have mentioned very clearly in the starting of this)

1) calculate the Timing Specification of a Block/Circuit/Library:

2) Calculate the Timing voilation in a ckt.

Please see the different inputs for both the case above on the blog.

I have given 2 example for both the cases.. and you can see that the way we are calculating the setup time and setup violations are different. same thing for Hold voilation and hold time.

Please see the check the part 3a and 3b for the referance. Still if you think something is not clear .. please let me know

6. thanku sir thankyou so much..this blog helped me a lot..I really appreciate your work

7. i am waiting for ur part 4-5....

8. Hi,

I am really Sorry for such a delay in posting other parts ... actually I become busy in my official work. I will try to post those one ASAP.
Please let me know your mail id- so that I will inform you once I will update my blog.

9. Hi,

I am a bit confused about the slack calculation in the first example. I think that it should be other way round.
For Hold time , Slack = 17ns - 18ns = -1ns and hence hold violation.
For Setup time, Slack = 26ns - 20ns = 6ns and hence no setup violation

10. Hi,
Its very simple and you are not suppose to confuse.
As I have mention in the last and also in previous part that

Hold Slack = Arrival Time - Required time (since we want data to arrive after it is required)

and in the first example- Arrival time is 18ns and Required time is 17ns, so it should be 18-17=1ns.

Let me know in case you are still confuse and it will be good if you explain the reason of that.

11. Hi,

Thanks for your response. I really appreciate for taking time and explaining me the process. Its my fault, I should have been more attentive before asking the question. Though this makes it real easy to understand. Good work on the article.

12. Hi,
I have a doubt regarding how delay is calculated along a path.i think there are two ways

1) to calculate max delay and min delay, we keep adding max delays and min delays of all cells(buffer/inverter/mux) from start point to end point respectively.

2)in other way, we calculate path delay for rising edge and falling edge separatly. we apply a rise edge at start point and keep adding cell delay. cell delay depends upon input transition and output fanout. so now we have two path delay values for rise edge and falling edge. greater one is considered as Max delay and smaller one is min delay.

which one is correct ?

13. Hi Lalit,
Nice question.. It very difficult to explain everything here.. so please refer next blog- just published. It will help you to understand several thing.

14. Awesome.. awesome.. your style makes things look very trivial.. thanku :)

15. Nice question..

16. Hey Can i hav ur email id..
hav few more doubts..
if its okay.

1. Please find from the Contact Me section.

17. hi i have one doubt.

y set up is fixed first then hold .

18. Hi
Thank you somuch for the detailed analysis.
I'm not sure if the clock period calculation is right. For the circuit to work, shouldnt the clock period be sum of U(7, 4, 2, 5, 6)? If not, can you pls clarify why?

Thanks again.

19. Hi,

You are correct half. :) .. See its a combination of sequential and combinational circuits. Since there are sequential circuits then there are several concepts - like multicycle path and all. So in that case you can't calculate the Clock period straight forward like sum of U(7,4,2,5,6). What ever you have mentioned .. its true only if there is no sequential device in between.. and there is a condition that you should get the output with in one clock pulse.

I hope you got my point.

1. obviously seq device must not present, it is basically seen betweeb two sequential devices

20. Hi , thanks for the information and please explain with the waveforms

1. I will try to do that sometime later. :)

21. Bahut bahut dhanyawaad aapkaa! Aap chiraayu hon!

22. I have a question.

Is there a typo in Problem2->Step3?
=( Hold time of Flipflop + Clk path max delay) - (A2D max delay)

... should be
=( Hold time of Flipflop + Clk path max delay) - (A2D min delay)

right?

1. Hi Lionel319,

You are right. Its Typo .. in above step its written min and delay value is also min. :)

Thanks for pointing this.

23. sir i'm waiting for the part 4 and part 5 ..these parts are very good... i really appreciate ur work...

1. Hi Suresh,

Thanks for appreciation.. In am in the process of posting few more parts but there are few more topics which are more important from STA point of view. So righ now working over that. I will suggest that you go through latest topic .. that will help you in STA concept a lot.

24. hi sir,
i hav a doubt that, is setup slack= RT-AT
and hold slack= AT-RT?

25. in the third problem, it seems to have many clk2out paths. why specifically this one is selected?

1. Hi,
Rest of the paths are not valid.. Means in rest of the paths there are more then 1 flip flop.

26. how to calculate max clk frequency
1/max(17 16)
how to cal ?

1. Hi Sridhar,
Max (17,16) means .. maximum value out of 17 and 16. So its 17.
so 1/max(17,16) = 1/17.
Now you can calculate this value. :)

2. thank you sir

3. Why is the max clock frequency = 1/ max(Tclk).
It should be min(Tclk) no???

27. sir tell sm good book for these timing concepts

I am completely out of touch from the book available in the market.So I am really sorry that I can't suggest you right now. But I will see If I can find out any book.

28. Hi,

y set up is fixed first then hold .
and why hold will not be checked in synthesis?

29. Dear Sir,

I really like all your post. First time i am feeling comfortable with timing analysis.......

"I have gone through the Altera ppt. & found that:- "Data Required time= clock required time - Tsu ", while the setup time definition we discuss is Tsetup= Td(max.)-Tclk.(min). Please let me know what exactly the relation is.........

1. its like ...

Setup Slack = Data Required time - Data Arrival time.

I hope you are looking for this..

30. great job. It was very helpful

31. hi

I am still having a small doubt in regards with the why hold is checked at the same clock edge ,

Data is launched but during hold check we are worried about the data whether it is stable after the capture clock edge , so need to worry about this capture clock edge only . need not to worry about when it is being launched.

During setup check , data is launched and it should be stable before the arrival of the capture pulse. so Launching the data and capturing of the data both are important and happens in different clock edges so Clock period will come into the picture and hence setup check will be done at the next clock edge

Can you comment on that ?

1. see .. try to understand the hold in this way..
who will disturb the stability of data once capture clock grab the data... ANS is .. some other data which is coming from behind.
so DataA started from launch clock at 0t... reached at capture clock at 5t. Now at 6t .. DataA is captured but DataB is launched. Now DataA can remain stable at the capture clock until DataB disturb the DataA(or say DataB reaches to capture clock.
Now for Hold if you want DataA should be stable for next 2t (means till 8t), then you want to make sure that the DataB should not reach at capture clock with in 2t (launched at 6t -- should not reach at capture clock at 8t).
So Now our concentration/worry is not DataA.. it become DataB..(means when the DataB is launched).

I hope now you got the point why we are worried about the data be launched for hold check.

About the setup -- you are absolutely right.

32. awesome explanation of the concept I have ever read ...

33. This all is really very useful. I think without studying this blog It has been kind of impossible for me to understand setup and hold concept

34. sir I have a doubt,wats the need of calculating clk2out delay. We require only maximum data to out delay for estimating clock frequency,why we are taking clock to output delay for frequnecy of opern. calculation........

35. Sir,

Could you please explain the clock period in the first example. How did you take it as 15ns?

1. hi priya,

I have assumed it for this example -- you can see later I have mention that if the Clock Period is 22ns then there will be no violation.

36. Sir,

In Question 1, I cannot undestand as to why you have added Hold Time while calculating Max. Clock path delay and similarly substracted Setup time while calculating Min. Clock path delay.... ??

Please reply ASAP , have an interview scheduled in some days .

first read the previous 2 parts for the reference..

Understand it Step by step..

1) Data should be stable after the clock edge (switching) for a certain time for not having hold violation( and this certain time is know as Hold time).

2) Assume that this hold time is fixed for a particular FlipFlop and its equal to "Th" sec.

3) Assume Clock edge (switching) is at "Tclk" sec.

4)It means if data changes between "Tclk" sec and "Tclk+Th" sec, then there is a hold violation.

5) This "Tclk" is calculated by the Clock path delay.

Now for hold violation we take "Max. Clock path delay" , so the hold time of the flip-flop is added in this time.

Same explanation for Setup also.

i hope I made my point clear. if still you have any confusion, please let me know.

2. THANKS A LOT SIR

37. Sir,

I have read in some link that setup time is considered in calculating the clock period.Can you please explain this?
I remember the explaination given in waveform?
And hats off to your blog !!

Thank you

1. Hi, Its already there in above blog. Looks like I didn't get your question clearly.

38. Sir,

I have one doubt in the 1st problem you have discussed.
When checking for violation for setup why have you considered the data path as
CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

should it not be
FF1/CLK ->FF1/Q ->Inverter ->FF2/D
as you have explained earlier in part 1 ??

1. first one is correct ...
CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

the reason we have added CLK->FF1/CLK .. when you are calculating the difference between the launch and capture clock, then CLK is your starting point. So you have calculated the clock delay from CLK and similarly data delay also be in the reference of CLK only.

I hope you got my point.

39. Exceedingly supper, we would like to see many more blogs like this..

40. Sir,
first of all i would like to thanks for such a great work.
but i m bit confused about the max Clock frequency(problem -2) - 1/max(reg2reg,clk2out,pin2pin).
Shouldn't only the combinational circuitry present between 2 ffs and the setup time of ff be considered for the max clock frequency ?? because if i cascade 2 ffs with a combinational logic between them , then the max clock freq would be " 1/(t-setup + t-comb_max + t-c2q) " basically 1/t-reg2reg . so even i put some more combinational logic ahead of ffs , the above clock will work .
Thanks

1. I am in the process of writing a seperate blog for calculating the clock frequency. Just wait few more days. I will post and let you know.

41. sir I have a doubt,wats the need of calculating clk2out delay. We require only maximum data to out delay for estimating clock frequency,why we are taking clock to output delay for frequnecy of opern. calculation........

1. I am in the process of writing a separate blog for calculating the clock frequency. Just wait few more days. I will post and let you know.

2. Please find the Blog on the "Maximum Clock Frequency" related issue here.

Maximum Clock Frequency

42. in the first problem, in setup calculation,in the clk path delay calculation,how to calculate CP n they taken 15,how is it?

1. Hi Shilpa,

this Clock Period = 15 .. is the part of problem statement/specification. You can see that's the reason I have mentioned that if its 22 then the case will be different.

43. Hello,

Any information on clock period checks in STA and in Extracted Timing Models?

Thanks and Regards,
Chetan B S

44. Hello,

Can you please let me know why in the example 1
So Hold Slack=Td - Tclk

I think it should be "TCLK(max)-Td(min)" mentioned in your previous blogs

Thanks
Sakshi

1. Hi Sakshi,

In the previous blog that was Hold Time .. And this is Hold Slack. I have discussed the both in this blog to remove the confusion. Please read the starting para before the example carefully and then check both the example.
Even after that if you find confusion.. please let me know. I will try my best to resolve your query.

45. Hello sir,

Really good blog.. Nice work:)

I have a doubt in question1:
Suppose there are setup and hold times for FF1,the should we include them in the calculation of Tclk..?
If no,whats the reason?

1. If you are talking about the FF1 - and that's the launch FF, then first of all - that will not be the path of Tclk. That will be the part of Td (data path delay).

Second thing - for setup and hold violation we calculate at the Capture FF.. so Capture FF's Setup and hold time matters in all the calculation.

I hope.. point is clear.

46. Hi Sir,

I gone through your "Set up and Hold time" part of the blog. I'm still confused sir,
My doubts are:

1) In first question, when finding the hold time violation you have calculated tclk including the hold time in it and then subtracted the tclk from td. My doubt is can I calculate tclk without including the thold and subtract the tclk from td and say that hold time violation occurs when the difference is not greater than 2(t hold)..?

2)In second question, when calculating the setup time for input A: For the max data path delay u have considered this "Tsu + (Tpd U7 + Tpd U3 + wire delay)".My doubt is why you didnt consider the tC2q delay in the above calculation. Also while finding the tclk min delay you have only considered 2ns from U8 ignoring the delays due to flipflop U2. Why was that done..?Frankly speaking i dont have the clarity regarding when to use TC2Q and Tsu and Th.

Sir, please reply ASAP,have an interview scheduled in few days.Clarity in these things will be really helpful.

1. Hi Sandeep,

First Come first-

Ans of 1 :

What ever you are saying in the first question is correct .. you can do it .. calculate the difference and say whether its less then or greater then Hold time or not and then decide whether there is a Hold violation.

I have explanied the same thing in my latest blog also.. Please refer that for the details...

http://www.vlsi-expert.com/2012/11/fixing-setup-and-hold-violation-static.html
and
http://www.vlsi-expert.com/2012/11/fixing-setup-and-hold-violation-static_20.html

For 2nd :

if I understood correctly - you want to ask about the following piece of information .. and remember this is specific to the following path..

A -> U7 -> U3 -> D of U1

A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns
See - If you will read the post once again then you will realize that there are 2 type of FFs. Capture FF and Launch FF. When you are calculating the Clock path delay -- then you consider the Tck2q delay of the launch FF. Not of the capture FF.
In the above case - U1 is the capture FF. So we will not consider the Tck2q delay of that in our calculation. I hope this point is clear.

regarding the second point - "Also while finding the tclk min delay you have only considered 2ns from U8 ignoring the delays due to flipflop U2."

Since in this path U2 is not in picture - there is no need for considering the delay of U2.

In the last I will say only one thing - Dnt try to remember the formulas - just remember the concepts- then you can automatically come to know where to use Tck2q and Tsetup and Thold.

Still in case you have any doubt - Please drop me a mail. I will try my best.

47. this blog is great.. it covers my number of things

48. sir,I am confused about the calculation of clock period (i.e 15 ns) for clock path delay in set up analyses.I agree that as set up time is checked in next cycle so previous clock period is also added but how did we calculate the revious clock period=15ns? please explain.
And my second question is that in calculating clock path delay for hold analysis we added hold time but for setup time analyses we are subtracting the setup time in clock path delay..why??please explain..
Thanks

1. Hi Divya,
I will suggest to read the other comment also. Some time it will help you to remove all your confusion. :) Anyways ..
this Clock Period = 15 .. is the part of problem statement/specification. You can see that's the reason I have mentioned that if its 22 then the case will be different

Now your second question was about the adding or subtracting the hold/setup value. The Reason we are subtracting the setup value because as per the setup defination .. "data should be stable setup time before the clock edge at the capturing FF" .. so before means we will subtract the setup time from the data_delay and then we will see whether it is satisfying the setup condition.

Same explanation for hold analysis.

2. thanx sir...i had the same problem...now its clear...

49. Thanks So much sir. :)

50. Hi VLSI,

I really enjoy going through your blog, you have done a great job.
I will appreciate if you can answer one query.

in problem2,step2 you wrote:
"
Step2: Find Out Setup Time:

A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)
= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)
= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8
= 3 + (1+8 ) - 2 = 10 ns
"

I am confused about the A2D max delay,
shouldn't it be Tpd U7 + Tpd U4 + Tpd U3 + Clock to Q delay of U2

1. I have the same doubt too.

also why is that min(clk path delay) considered in the first place.
Since the skew is 0 (U2 goes to the launch and capture flop). please reply asap.

2. Hi guys,

A2D max delay is considered as the max delay of data path between A and any D point of both the Flip Flops. So we consider only that path which has the max delay.

52. You said we need to take max path for clock to out path in Problem 2. But when you asked to add registers/buffers which is continuation to the prob 2, looks like you have not picked up max path for clk to out. can you explain why?

1. Similar question but with respect to input to reg path was asked in the post ..

maximum-clock-frequency-static-timing

Please check that one and if still has doubt then let me know.

53. why you are not considering In2reg path in calculating Max frequency ?

1. I have replied similar type of question in the previous part..

maximum-clock-frequency-static-timing

54. sir, in second example u hav not mentioned min/max delays associated with components, but if there will be min/max delays given then how to solve the example? m not preety clear abt it....plz help

1. Its similar to problem no 1. Just where you have to calculate the max .. and min delay of path by choosing max and min delay of components.

55. thanks for useful sharing!!!

56. can anyone tell me why we take min delay in clock path and max delay in data path during setup slack?

1. I have replied similar type of question in the previous part..

maximum-clock-frequency-static-timing

57. Firstly, Pretty good blog :)

I have a doubt with respect to problem 2: Setup Time calculation:

If I have understood correctly, then
Datapath is a path which has start point as either input port or clock pin of FF and has end point as data input pin of FF or output port of design.

In this question no 2. Why are these paths are not datapath? You have considered only 2 data paths.

a) A->U7->U5->U6->Y (Async path)
b) U2/C->U5->U6->Y
c) U2/C->U3->U1
... Similarly others.

Thanks
Vikram

1. Hi Vikram,

I have mentioned in my few previous comments also. I would say you try with them and let me know in case any difference are there in the results.
Consider this an exercise for you. :)

58. thanks for the detailed explanation...

59. sir first of all thanks for a wonderful post
i just wan to know how have you calculated clock to out delay in the 3rd problem (which is 13) . Why have you not considered c2q delay of u8 ff, delay of AND gate , and clock delay of u9 flip flop

1. What the exact path ?? Can you do the calculation and let me know. I will check on my end and if its looks to me that it's perfect I will change my calculation.

60. really thanx for such a nice blog,
sir plzz tell me that in first ques while calculation clock delay for hold voilaton checking why u add thold to d given eq and while calculation set up violation why u subtrat set up time frm given eq

61. First of all thanks sir for the wonderful post on timing analysis, it is indeed very lucid.

Sir i have a doubt in ques 2. it is asked "what should be the Setup and Hold time at Input A" ?.
Sir correct me if i am wrong but setup and hold are calculated for sequential circuit so what does it mean to calculate at the input ??

62. you done awesome work.. i have on doubt. in problem 2 while calculating maximum frequency you taken inverse of maximum delay of three delays.. i think it is minimum..

63. sorry i understood that is maximum only.. you are right...

64. Sir can you please explain why is setup time off flip flop added when computing the register to register delay in problem 2

65. This comment has been removed by a blog administrator.

66. This comment has been removed by a blog administrator.

67. This comment has been removed by a blog administrator.

68. This comment has been removed by a blog administrator.

69. This comment has been removed by a blog administrator.

70. This comment has been removed by a blog administrator.

71. This comment has been removed by a blog administrator.

72. This comment has been removed by a blog administrator.

73. Hello Sir,
If there is a hold violation found after a design has been taped out, will the chip work properly? Or is there any remedy for this situation?

74. In part 3a you said
Setup time = Td(max) - TClk(min)
hold time = TClk(max) - Td(min)
while in problem 1 you have used
setup slack = Tclk - Td
abd Hold slack = Td - Tclk
why the formula is changed in problem 1?

1. If you read carefully then you come to know that in part a - we are talking about "How to calculate the setup Time" but above we are talking about the "Setup slack" which help to calculate the Setup violation. Try once again to read both with this view, if still you think there is any confusion - Please reply me back.

2. ya sir... still i am confused with the same calculations.. plz help me out ASAP...

3. hi Chandrakanth,

Please let me know what's your confusion. As I have mentioned that there 2 things are different. In one case, we are talking about how Setup time is calculated and then this Setup time become part of Flipflop Specification. In second case, we are talking about - setup Slack. Means Setup time of Flipflop is fixed (which came from the first Case), now we are trying to calculate if given circuit meets the Setup requirement of Flipflop or not.

Please let me know if above description helps you. If still Any confusion - please help me to understand where is the confusion. and what's the confusion ?

75. The contents are good but the grammar could be made better for an user to get a clear understanding of the concepts. Also the contents have to better organized to avoid confusions. I got confused in problem 1 on where clock period of 15ns is defined. The "Note" section that is put above clock delay calculation section should ideally be put after the calculation as it is misleading, that user will take to be the "Note" section for the previous data path delay calculation.

76. Awesome blog for timing related concepts. Explained in the best possible manner.

77. When we talk about finding the max frequency, for the reg2reg component we should consider clock adjustment if there is a skew b/w the clock of launch and capture ff's. Am I correct? Also, going with this method, in the 3rd problem, if we put a 2ns buffer just before clk pin of U9 and a 0.5ns buffer just before clk pin of U1, the maximum freq. should increase to 64.5 Mhz. Am I correct? Please clarify.

Thanx

78. From where and how would we get the tmin and tmax values?

79. hi... For calculating maximum frequency, we need to consider input to register path too right?? coz in ur solution to that paricualar question u have not included input to regiater path... please clarify this...

80. Hi,
can you Please elaborate why setup time of FF2 is subtracting in last problem for setup analysis and holding is adding.

81. This comment has been removed by the author.

82. This comment has been removed by the author.

83. sir , I have a doubt
why setup is calculated for next clock cycle and hold is calculated for same clock cycle

84. please explain why setup time is subtracted in the first problem while calculating min clock path delay

85. Hi, I have one doubt in 2nd question for finding Maximum Frequency.

In your earlier post you have mentioned that there are 4 timing paths:
1. Input pin/port to Register(flip-flop)
2. Input pin/port to Output pin/port
3. Register(flip-flop) to Output pin/port
4. Register(flip-flop) to Register(flip-flop)

And maximum frequency at which circuit should operate is 1/(max delay out of above four timing paths).

My doubt is that why have you considered clock to output path. Shouldn't it be Register (clock pin of FF) to output path?? and if that's the case then delay of cell U8 should not be taken into consideration.

Thanks!

1. similar doubt about max clk frequency:
I understand that clk frequency must meet the FFs' requirements on timing.
Why it also needs to meet clk to output path and pin to pin path in the 2nd problem?

86. Hi sir,
after completion of first and second question , in points to be remember section there is little bit confusion in clock2out delay in caliculating maximum clock frequency, in 2nd question clock2out delay is caliculated by U8+TC2Q OF U2 + U5+ U6, but in points to be remembered section for the ckt which you have taken as example for that it should be buffer delays+TC2Q of FF2, but you have taken Clk2Out Delay = Clock delay w.r.t FF (max) + clock­to­Q delay of FF1 (max) + comb. delay (max)

thanks
meharaz

87. This comment has been removed by the author.

88. please somebody explain me what actually is "MAXIMUM CLOCK FREQUENCY", which paths do we have to consider??...

89. Such horrid English. Besides in 1st sum you are contradicting to what you mentioned in previous blogs. As per previous blog Setup Time = Td(max) - Tclk(min). As per the 1st example you have done it the other way round. I am a newbie to these concepts and confusing people like me is just not right.

90. Hi,

First of all, amazing work. Hats off to you!

I just have a single doubt.
In the final 'Points to remember' section, under 'Calculation of maximum frequency' will the Clk2out not be,

Clk2out = Clock delay (of CLKB w.r.t CLK due to the buffers) + clock to Q of FF2 ?

The path, CLK --> FF1 --> combo ends at FF2. Shouldn't the Clk2out path start from a clock source and end at the output pin ?

91. I read some articles on this site and I think your blog is really interesting and has great information. Thank you for your sharing.
windows movie maker

92. Hi!
Great blog. Just one doubt
In ques 3 why is the max clk to out path not taken?? You have considered the path with min delay. why so?

1. There is only one clk2out path. The other max path which you mean ends at D of U9,DFF which means it's not a valid clk2out path.

93. This comment has been removed by the author.

94. Why Hold time is frequency independent and setup time is frequency dependent ?

95. Sir,
I have confusion on the calculation of Clk-to-Out delay of Question 3.
Why the maximum clk-to-out path is not taken ?
Can't we consider the Tc2q delay of two DFF's in a single clk path ?
I mean is clk path always considered through one DFF only ?

96. Yes, the article I was looking for. Your article gives me another approach on the subject. I hope to read more articles from you.

97. How the setup and hold time equations will be at pre-cts and post-cts stages?

98. Just one question -
In the second example, we had calculated the required hold time at A. It came out to be negative. Is this a violation?

My understanding is that there is no requirement of "holding" the signal for some time and that the signal can switch as it already is. If this is correct, why is there a need to improve the timing of the circuit, as in example 3.

Please correct where I am wrong.

99. hi sir
really its gud
but i got one doubt that if hold time is positive then hold slack will be negative, is this correct or not?
plz response

100. What is effect of IR drop on the setup and hold time?
What is the relation between the rise, fall time and setup, hold time?

101. what is the effect of IR drop on setup time and hold time?
what is the relation between the rise, fall time and setup, hold time?

102. Can you please show the waveform for the given explanation of the hold violation and setup violation for the given example, with explanation? It would be great help if you do so, I could not relate the calculations to the results.

103. Hi, very nice post. However I am not able to understand one thing. I your post 3a, you mentioned
setup violation = Data(max)-Clk(min) and hold violation=Clk(max)-Data(min). In post 3c, it is completely opposite. Can you explain this?

104. Great work sir!
In step 4 of problem 3 while calculating the clock to output time why did we ignore Tc2q of U1 or Tpd of U5?
As we have to find the maximum clock to output time, don't we have to consider all the paths from clock to output. I know I am going wrong somewhere in my thinking but can't figure out where.

105. Hi sir,
Let's consider in first problem if we have one common buffer for both launch and capture paths..then what is your analysis

106. Hello sir, your post is really helpful for understanding things the right way. I have one doubt. In setup time violation clock period is added to calculate Tpd(clk)min. I understood that, But why is not necessary to add the clock period to Tpd(clk)min while calculating the setup time of an Input ? Please clarify on this

107. hello sir,
In prob 2, can you pls explain what is meant by setup time of Input A?

108. There are some questions about question number two.

First, what is the significance of obtaining the maximum period of the clock? That circuit works as a matter of course when the clock cycle is slow. Slowing down the cycle is not a problem at all. Shouldn't we get a minimum period?

Second, delays in U8 are not considered at all. Because it applies equally to both flip flops.

Third, there is a delay for each unit, and if the input signal does not change during the process of each unit's output signal, each unit will normally produce the output result. Thus, by my calculation, the maximum delay time of step4 is 9 ns of U5. (equivalent to the pipeline)

What do you think of this opinion?

109. As you have written:

When a hold check is performed, we have to consider two things-
Minimum Delay along the data path.
Maximum Delay along the clock path.

110. Hi sir, I really appreciate the effort put in here. Post are really helpful.
I need one clarity on setup time and hold time equation that you posted in this problem and 2 pages previous to it where you defined setup and hold with respect to Td and Tclk. 2 pages back Hold slack is mentioned as Tclk-Td but here in problems1 hold slack is taken as Td-Tclk. This is causing contradictions. Can you clarify me on this please.

1. Hold time calc and Hold slack calc are different things.

111. hi,
how did you calculate clock period in first example?