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Monday, September 24, 2012

Maximum Clock Frequency : Static Timing Analysis (STA) basic (Part 5a)

STA & SI:: Chapter 2: Static Timing Analysis
2.1 2.2 2.3a 2.3b 2.3c 2.4a
Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b
Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2
2.6c 2.7a 2.7b 2.7c 2.8
Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

This is a general question in most of the interview, what’s the maximum clock frequency for a particular circuit? Or Interviewer will provide some data and they will repeat the same question. Many of us know the direct formula and after applying that we can come across the final “Ans” but if someone twist the question. Some -time we become confuse. I motivation of this blog is the same. Several people asked me how to calculate the max-clock frequency. So I thought that it’s best if I can write something over this.

Here I will discuss the same but from basic point of view. It has 3 major sections.
  1. In 1st section, we will discuss different definitions with respect to Sequential and combinational Circuits.
  2. 2nd Section contains the basics of “Maximum Clock Frequency”. I will explain why and how you can calculate the max Clock frequency.
  3. I will take few examples and try to solve them. I will make sure that I can capture at least 2-4 examples from easy one to difficult one.

As we know that now a days all the chips has combinational + sequential circuit. So before we move forward, we should know the definition of “Propagation delay” in both types of circuits. Please read it once because it will help you to understand the “Maximum Clock Frequency” concepts.

Propagation Delay in the Combinational circuits:

Let’s consider a “NOT” gate and Input/output waveform as shown in the figure 

From the above figure, you can define
  • Rise Time (tr):  The time required for a signal to transition from 10% of its maximum value to 90% of its maximum value.
  • Fall Time (tf):  The time required for a signal to transition from 90% of its maximum value to 10% of its maximum value.
  • Propagation Delay (tpLH, tpHL):  The delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value.
I want to rephrase above mention definition as
  • This value indicates the amount of time needed to reflect a permanent change at an output, if there is any change in logic of input.
  • Combinational logic is guaranteed not to show any further output changes in response to an input change after tpLH or tpHL time units have passed.
So, when an input X change, the output Y is not going to change instantaneous. Inverter output is going to maintain its initial value for some time and then it’s going to change from its initial value. After the propagation delay (tpLH or tpHL - depends on what type of change- low to high or high to low), the inverter output is stable and is guaranteed not to change again until another input change ( here we are not considering any SI/noise effect).

Propagation Delay in the Sequential circuits:

In the sequential circuits, timing characteristics are with respect to the clock input. You can correlate it in this way that in the combinational circuit every timing characteristic/parameter are with respect to the data input change but in the sequential circuits the change In the “data input” is important but change in the clock value has higher precedence.  E.g in a positive-edged-triggered Flip-flop, the output value will change only after a presence of positive-edge of clock whether the input data has changed long time ago. 

So flip-flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive edge-triggered) or falling (for negative-edge triggered) clock edge. 

Note: Setup and hold time we have discussed in detail in the following blogs. Setup and Hold part1; Setup and Hold part2; Setup and Hold part3 . But just to refresh your memories :) , I have captured the definition here along with “propagation delay”.

Let’s consider the positive-edge flip-flop as shown in figure.

Propagation delay, tpHL and tpLH , has the same meaning as in combinational circuit – beware propagation delays usually will not be equal for all input to output pairs. 

Note: In case of flip-flop there is only one propagation delay i.e tclk-Q (clock→Q delay) but in case of Latches there can be two propagation delays:  tClk-Q  (clock→Q delay)  and tD-Q (data→Q delay). Lation delay we will discuss later.
So again let me rephrase the above mention definition

  • This value indicates the amount of time needed for a permanent change at the flip-flop output (Q) with respect to a change in the flip flop-clock input (e.g. rising edge).
  • When the clock edge arrives, the D input value is transferred to output Q. After tClk−Q (here which is equivalent to tpLH), the output is guaranteed not to change value again until another clock edge trigger (e.g. rising edge) arrives and corresponding Input also.
Setup time (tsu) - This value indicates the amount of time before the clock edge that data input D must be stable.
Hold time (th) - This value indicates the amount of time after the clock edge that data input D must be held stable.
The circuit must be designed so that the D flip flop input signal arrives at least “tsu” time units before the clock edge and does not change until at least “th” time units after the clock edge. If either of these restrictions are violated for any of the flip-flops in the circuit, the circuit will not operate correctly. These restrictions limit the maximum clock frequency at which the circuit can operate (that’s what I am going to explain in the next section J )

The Maximum Clock Frequency for a circuit:

I hope you may be asking that why there is a need of explaining the combinational circuit propagation delay here. Combinational circuit is always independent of clock, so why combination circuit here. J
Now the point is combinational circuit plays a very important role in deciding the clock frequency of the circuit. Let’s first discuss an example and try to calculate the circuit frequency, and then we will discuss rest of the things in details. J
Note: Following diagram and numbers, I have copied from one of the pdf downloaded by me long time back. 

Now let’s understand the flow of data across these Flip-flops.

  • Let’s assume data is already present at input D of flip-flop A and it’s in the stable form.
  • Now Clock pin of FF (Flip-Flop) A i.e Clk has been triggered with a positive clock edge (Low to high) at time “0ns”.
  • As per the propagation delay of the sequential circuit (tclk-Q), it will take at least 10ns for a valid output data at the pin X.
    • Remember- If you will capture the output before 10ns, then no one can give you the guarantee for the accurate/valid value at the pint X.  
  • This data is going to transfer through the inverter F. Since the propagation delay of “F” is 5ns, it means, you can notice the valid output at the pin Y only after 10ns+5ns=15ns (with reference to the positive clock edge- 10ns of FF A and 5 ns of inverter)
    • Practically this is the place where a more complex combinational circuit are present between 2 FFs. So in a more complex design, if a single path is present between X and Y, then the total time taken by the data to travel from X to Y is equal to the sum of the propagation delay of all the combinational circuits/devices. (I will explain this in more detail in the next section with more example)
  • Now once valid data reaches at the pin Y, then this data supposed to capture by FF B at the next clock positive edge (in a single cycle circuit).
    • We generally try to design all the circuit in such a way that it operates in a single clock cycle. Multiple clock cycle circuit are special case and we are not going to discuss that right now (as someone says – it’s out of scope of this blog J )
  • For properly capturing the data at FF B, data should be present and stable 2ns (setup time) before the next clock edge as part of setup definition).
So it means between 2 consecutive positive clock edge, there should be minimum time difference of 10ns +5ns +2ns = 17ns. And we can say that for this circuit the minimum clock period should be 17ns (if we want to operate the circuit in single clock cycle and accurately).
Now we can generalize this
Minimum Clock Period = tclk-Q (A) + tpd (F) + ts (B)
And “Maximum Clock Frequency = 1/(Min Clock Period)”

Now at least we have some idea how to calculate the Max clock frequency or Min Clock Period. So even if we will forget the formula then we can calculate our self and we can also prove the logic behind that. Let me use the same concept in few of the more complex design circuit or you can say the practical circuit.


  1. Isn't the output of not gate supposed to be inverted?

  2. This comment has been removed by the author.

  3. Hi
    while defining set-up/hold time in the previous blogs it is assumed that data/clock will arrive late due the delay form actual input to D(FF)/clk(FF).if the delay is already specified (as in the above problem for calculation of max clock) do we need to consider the set-up of FF again.
    is that the delay specified is varying?
    please clarify..

  4. Hello..

    Tclk-q + Tcomb - Tsu <= Tclk to avoid setup violation.

    So, Max frequency calucation -> Tclk-q + Tcomb - Tsu (this will give the clock period of the max freq clock)
    Hence, 10+5-2 = 13 is the period & 1/13 is the frequency.

  5. ignore prev comment...
    It should be Tclk-q + Tcomb + Tsu <= Tclk, so your calculation of 10+5+2=17 is correct

  6. Hi,
    In you have used Max Freq=1/Max(Time) here you have mentioned 1/Min(time) . I guess the 2nd one is write.

    1. setup eqn
      Tcomb(max) + Tc2q(max) + Tsu >= Tclk + Tskew(min)(assuming +ve skew)
      data path delay(max) = clock period(min)
      here he is talking about clock period, in previous blog he talked about data path delay
      both are correct as both are same

  7. Hello Sir,

    Can you please post a detailed explaination on the Effect of Jitter on the Setup and Hold time requirements.

    I read somewhere that Jitter effects only Setup but not Hold time. But I don't know Why it is...

    Will you please help me to figure it out.

  8. hello,can u please explain how to calculate overall frequency of the system,if it operates at different frequencies

    1. If its operate at different frequency ...then you have to mention all of them. but just in case you need only 1 frequency ... then you have to see what's the input clock frequency of the system. Inside the system... whatever you do with that frequency (double or half), no one care about that.

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