## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## Wednesday, January 8, 2014

### Effect of Threshold voltage: Static Timing Analysis (STA) Basic (Part-7c)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

#### Effect of Threshold voltage on the propagation delay and transition delay:

If you will see the below equations – I am sure you can easily figure out how threshold voltage effect the cell delay. (Note: Below Resistance formula is with respect to NMOS. You can derive similar formula for PMOS also (Just replace subscript “n” with “p” J ).

From above equation we have following points
• On Resistance of MOS is inversely proportional to the “VDD-VTn” (where VTn is Threshold Voltage).
• Decreasing the threshold voltage (LOW VTn) increases “VDD-VTn” for constant VDD.
• Increasing “VDD-VTn” means decreasing “On Resistance” Rn.
• Decreasing Rn à RC decreases.
• Means large Driving capability (Ability to source or sink current)
• Decrease the time to charge the output load (capacitance) (Consists of  source/drain capacitance of the driving gate, the routing capacitance of wire, and the gate capacitance of the driven gate) **
• Means “Output Transition time of Gate A” and “Input Transition time for Gate B” decreases.
• Decreasing the transition time means decreases the propagation time.

So we can say that…
"Delay can be reduced by using low Vt cells, but the cost paid is high leakage power"
Direct effect is that low Vt cells are often more leaky i.e. leakage power increases.
If still you have any confusion below diagram should clarify your doubts.

I hope above diagram should clear your doubts about the effect of Threshold voltage on Delay.

In the next post we will summarize/list down all the methods of fixing the setup and hold violations.

1. Decreasing “VDD-VTn” means decreasing “On Resistance” Rn.
Doesnt decreasing this increase On resistance since its in the denominator?

1. Corrected ... It was typo..

2. That's sound like very educative lesson for me. I've been studying on electrical subject and this lesson of Static Timing Analysis (STA) Basic (Part-7c) really makes me knowledgeable. So thanks a lot :)

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