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Monday, November 27, 2017

Metal Wire Orientation (HVH or VHV)


In previous articles, we have discussed a lot about type of metal wire like Mx, My and others. We have also discussed about the Metal stack like 6 Metal layer stack : M1_3Mx_My_Mz. (If you have confusion, please refer Article "Metal Layer Stack Nomenclature").

In this article, we are going to understand another important concept: "Metal layer Orientation". Actually during routing of design, we use a terminology "Preferred Routing Direction" of Metal layer. May be you have heard HVH or VHV routing strategy. Even if not - then I am sure you have seen below fig somewhere :) .


In the above pic, you can see that M1, M3 & M5 are in Horizontal direction and M2 & M4 are in vertical direction. Still confused ??? :) Let me help you.

Metal wires in our design are at different levels. If, I assume that M1 is at first level then M2 is at second level, M3 at third and so on. Type of Metal (Mx, My, Mz) depends as per Metal Stack you are going to choose for your design. (For more detailing about the Metal stack - please refer Article "Metal Layer Stack"). By now, you should be clear that different metals present at different height with respect to substrate.

Now, only one question is remaining, how we are going to route these metals? How in the sense - in which direction or say orientation. Is/are there any standard/s behind this or user can route these metals wires as per their requirement? Very short answer of this question - There are standards or say recommendation for routing Metal wires. Timing is very critical now a days. From metal wires point of view - capacitance between them plays a very important role. (Note: Delay has relationship with RC constant - and this C is because of Capacitance between the wires). So as a designer we have to understand or say use those technique which can minimize these unwanted Capacitance (Remember - capacitance between Wires are always unwanted. It's always has side effect in negative sense :) ). To understand different type of capacitance between wires, you can refer Article "Basic of Capacitance & Resistance (from VLSI Point of view)"

Capacitance between 2 plates depends on area of plates parallel to each other OR I can say overlap area between 2 metal wires. During Routing - there are 2 extreme routing methodology.
  1. Parallel Routing Grid
  2. Cross Routing Grid


If we place metal wire on these routing grids (as an example - just picked only 2 wires of same metal layer), you can easily understand the concept of overlap area. Remember, right now we are talking about Ground cap (or Area cap) and not Coupling cap.


Parallel Metal Wire Orientation:

In the below figure, I have tried to show arrangement of capacitance between parallel metal wire between metal layers of different levels Like capacitance between M1 and M2. Since M1 and M2 both are parallel to each other 100%, Capacitance between them has dependency on width and length of the wire. This arrangement gives maximum Ground cap (Area cap).
Note: We are not discussing the capacitance between same type of metal layers (Between M1 and M1) known as Coupling Capacitance.


Cross / Perpendicular Metal Wire Orientation:

In the below figure, you can see that overlap area between M1 and M2 is only at their cross-section. This overlap area depends on their corresponding width parameter. You can see that their is no dependency on length of the wire. This arrangement gives minimum Ground cap (Area cap).
Front view and Side view of this arrangement helps you to understand this routing methodology more closely.


You can see that if we want to reduce the CAP then orientation of the Metal wire is very important. Cross (perpendicular) metal wire orientation gives minimum capacitance and that's the reason it's recommended. One of the direction is considered as Horizontal and other as Vertical. That's the reason - these orientation is known as HVH or VHV orientation (and corresponding routing strategy as HVH or VHV routing methods).

Saturday, November 25, 2017

Delay Interview Questions (Part 2)


In the last part (Delay Interview Questions: Part 1), we have discusses 2 scenarios
  1. Min & Max Delay Between 2 points having multi-paths when Delay are given as absolute number.
  2. Min & Max Delay between 2 points having multi-paths when Delay are given as Rise and Fall delay.
We have discussed these concepts from Interview point of view.
Note: Example 1 and Example 2, we have already discussed in last article.

Example 3:


Note: Above figure is same as in Example 1 and Example 2 (with small addition).

All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay:
                  Arc a1 -> y1 = (1.25ns, 1.5ns)
                  Arc b1 -> y1 = (1.1ns, 1.9ns)
OR gate (min, max) delay:
                  Arc a2 -> y2 = (0.3ns, 0.4ns)
                  Arc b2 -> y2 = (0.5ns, 0.9ns)

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is almost equal to the example 1 but with slight modification. Now, we are talking about the different input and output combination of AND gate. Remember, every input and output combination has it's own delay value. When we talk about the Delay of a Gate and if it's not related to input and output combination, it means we are talking about Boundaries of overall gate delay. To understand this concept - you need to revise or say understand Timing Arc concepts. Please read article Timing Arc and Unate: Timing Arc.

Intension of this question is to get more accurate delay value based on Path base analysis.
Note: Delay calculation in such circuit are of 2 type - Path base Analysis and Graph Base Analysis. You can get more detail about this in Article - Path Base Vs Graph Base Analysis: Part 1.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

In the above figure, you can see that
Path 1: Q1 -> Inverter -> b1 -> y1 -> Buffer -> a2 -> y2 -> Buffer -> D2
Path 2: Q1 -> Inverter -> Inverter -> Inverter -> b2 -> y2 -> Buffer -> D2


In Path 1:
b1 -> y1 is basically part of AND gate and during delay calculation we will use delay value as per Arc b1 -> y1 = (1.1ns, 1.9ns).
a2 - > y2 is basically part of OR gate and delay values are as per Arc a2 -> y2 = (0.3ns, 0.4ns).

In Path 2:
b2 - > y2 is basically part of OR gate and delay values are as per Arc b2 -> y2 = (0.5ns, 0.9ns).

Solution:
Path 1 (Min Delay) : 0.25 (inverter) + 1.1 (b1 -> y1) + 0.1 (buffer) + 0.3 (a2 -> y2) + 0.1 (buffer) = 1.85ns
Path 1 (Max Delay) : 1.00 (inverter) + 1.9 (b1 -> y1) + 0.2 (buffer) + 0.4 (a2 -> y2) + 0.2 (buffer) = 3.70ns

Path 2 (Min Delay) : 0.25 (inverter) + 0.25 (inverter) + 0.25 (inverter) + 0.5 (b2 -> y2) + 0.1 (buffer) = 1.35ns
Path 2 (Max Delay) : 1.00 (inverter) + 1.0 (inverter) + 1.0 (inverter) + 0.9 (b2 -> y2) + 0.2 (buffer) = 4.1ns

Overall Min Delay between Q1 and D2 = 1.35ns (From Path 2)
Overall Max Delay between Q1 and D2 = 4.1ns (From Path 2)


Example 4:


All Buffer has same delay:
                  Tphl (min, max) = (0.1ns, 0.18ns)
                  Tplh (min, max) = (0.15ns, 0.20ns)
All NOT Gate has same delay:
                  Tphl (min, max) = (0.25ns, 0.75ns)
                  Tplh (min, max) = (0.5ns, 1.0ns)
AND gate delay:
        Arc a1 -> y1:
                    Tphl (min, max) = (1.25ns, 1.5ns)
                    Tplh (min, max) = (1.3ns, 1.75ns)
        Arc b1 -> y1
                    Tphl (min, max) = (1.0ns, 1.9ns)
                    Tplh (min, max) = (1.1ns, 2.0ns)
OR gate (min, max) delay:
        Arc a2 -> y2:
                    Tphl (min, max) = (0.3ns, 0.35ns)
                    Tplh (min, max) = (0.31ns, 0.4ns)
        Arc b2 -> y2:
                    Tphl (min, max) = (0.51ns, 0.9ns)
                    Tplh (min, max) = (0.5ns, 0.75ns)

Note:
Tphl = Propagation Delay High to Low
Tplh = Propagation Delay Low to High

Question: Find out the Tplh and Tphl at point D2 with respect to Input Q1?

Explanation:
For this you need to understand the concepts of Tphl and Tplh. I am assuming that you know this part. Here we have to understand how different waveform (Rising input or Falling input) is going to behave in this circuit.

There is a little bit change in the picture of Path 1 and Path 2 (in compare to Example 1 and Example 2).

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):
  • Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
  • AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of AND gate for ARC b1 -> y1 => (1.0ns, 1.9ns)
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)
  • OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC a2 -> y2 => (0.3ns, 0.35ns)
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tphl.
Minimum Tphl at D1 through Path 1 = 0.25ns + 1.0ns + 0.1ns + 0.3ns + 0.1ns = 1.75ns
Maximum Tphl at D1 through Path 1 = 0.75ns + 1.9ns + 0.18ns + 0.35ns + 0.18ns = 3.36ns

Falling Signal Analysis (For Path1):
  • Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
  • AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of AND gate for ARC b1 -> y1 => (1.1ns, 2.0ns)
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)
  • OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC a2 -> y2 => (0.31ns, 0.4ns)
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path1. So in this scenario, delay between Q1 and D1 through Path1 = Tplh.
Minimum Tplh at D1 through Path 1 = 0.5ns + 1.1ns + 0.15ns + 0.31ns + 0.15ns = 2.21ns
Maximum Tplh at D1 through Path 1 = 1.0ns + 2.0ns + 0.20ns + 0.40ns + 0.20ns = 3.80ns

Rising Signal Analysis (For Path2):
  • Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
  • Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
  • Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
  • OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of OR gate for ARC b2 -> y2 => (0.51ns, 0.9ns)
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Tphl of Buffer gate => (0.1ns, 0.18ns)

For Rising Signal at the Input (Q1), we are getting Falling Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tphl.
Minimum Tphl at D1 through Path 2 = 0.25ns + 0.5ns + 0.25ns + 0.51ns + 0.10ns = 1.61ns
Maximum Tphl at D1 through Path 2 = 0.75ns + 1.0ns + 0.75ns + 0.90ns + 0.18ns = 3.58ns

Falling Signal Analysis (For Path2):
  • Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
  • Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Tphl of NOT gate => (0.25ns, 0.75ns)
  • Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Tplh of NOT gate => (0.5ns, 1.0ns)
  • OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of OR gate for ARC b2 -> y2 => (0.5ns, 0.75ns)
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Tplh of Buffer gate => (0.15ns, 0.20ns)

For Falling Signal at the Input (Q1), we are getting Rising Signal at the Output (D2) through Path2. So in this scenario, delay between Q1 and D1 through Path2 = Tplh.
Minimum Tplh at D1 through Path 2 = 0.50ns + 0.25ns + 0.50ns + 0.50ns + 0.15ns = 1.90ns
Maximum Tplh at D1 through Path 2 = 1.00ns + 0.75ns + 1.00ns + 0.75ns + 0.20ns = 3.70ns

Solution:
Through Path 1 (Min Tplh) : 2.21ns
Through Path 1 (Min Tphl) : 1.75ns

Through Path 2 (Min Tplh) : 1.90ns
Through Path 2 (Min Tphl) : 1.61ns

Through Path 1 (Max Tplh) : 3.80ns
Through Path 1 (Max Tphl) : 3.36ns

Through Path 2 (Max Tplh) : 3.70ns
Through Path 2 (Max Tphl) : 3.58ns

Overall Minimum Tplh at D2 (when input is at Q1) = 1.90ns (Through Path 2)
Overall Maximum Tplh at D2 (when input is at Q1) = 3.80ns (Through Path 1)
Overall Minimum Tphl at D2 (when input is at Q1) = 1.61ns (Through Path 2)
Overall Maximum Tphl at D2 (when input is at Q1) = 3.58ns (Through Path 2)

In Summary, I can write, At D2 with respect to Q1 Tphl = (1.61ns, 3.58ns) & Tplh = (1.90ns, 3.80ns)

Is it done? I mean do you think Interviewer is going to stop at this point. :) :) Don't ever think. By now they will realize that you are good in below concepts.
  • Min and Max Delay Calculation
  • Delay calculation based on Timing Arc (I can say some part of Path base & Graph base analysis)
  • Tphl and Tplh based Delay Calculation
  • Multipath Delay Calculation
  • Use of Rising edge and Falling Edge at Input during delay calculation

Now, it's time to check few more concepts related to CELL Delay (Like Cell Delay as a function of Input Transition Vs Output Load) and then how you can use those concepts in delay calculation of Combinational Circuit. :) Lets discuss this in Next Article.


Tuesday, November 7, 2017

Path Base Analysis (PBA) Vs Graph Base Analysis (GBA) - part1

Today, we are going to discuss about the Path base analysis Vs Graph base analysis. As such difference is more complex compare to what I am going to explain, but right now it's sufficient to start with. :)

Let's you have a combinational path with Net delay (min, max) and Cell delay (As per the Timing Arc). If, you have any confusion with respect to the timing arc, please refer below articles.
In the below figure, you can see AND gate (1) has 2 input, so 2 set of input-output delay combination.
  • Min Delay = 0.5ns, Max Delay = 1.5ns
  • Min Delay = 0.2ns, Max Delay = 1.2ns
Similarly, for other logic gates.


Now, if I will ask you to calculate the delay between point A and point B, then the concept of PBA and GBA comes into the picture. Before, I explain you this concept, please refer below few figures and then see the difference between PBA and GBA.



I am sure, if you have notice closely, then you have already realized the difference. :) But still let me highlight that.

In GBA (Graph Base Analysis), in place of choosing 2 combinations of AND gate (1) delay, i.e. (Combination_1: 0.5ns, 1.5ns ; Combination_2: 0.2ns, 1.2ns) we choose extreme boundaries, i.e. min delay = 0.2ns and max delay = 1.5ns.

In case of PBA (Path base Analysis), we are using actual delay between input pin and output combination (means choosing both combination of delay).
  • Combination_1: 0.5ns, 1.5ns
  • Combination_2: 0.2ns, 1.2ns

Note: Check the similar difference for AND gate (2) also.

You might be thinking that this is not accurate (means why in GBA we missed 2 value), we are adding unnecessary delay in our calculation. And I am glad to say that you are right. :) The reason we are doing this because from tool point of view - doing analysis or say calculation as per GBA is very fast compare to PBA. Runtime of tool is very low. And only difference is that we are adding pessimism in our calculation.

Now, if you want to understand the calculation of delay between different input pin (A, B, C) and Output Pin (Y), please check below figures.

Note: For clarity purpose (used different color combination) - I did this calculation and pasting in the form of picture. :)

Delay Calculation in Case of GBA (Graph base Analysis).


Delay Calculation in Case of PBA (Path base Analysis).


Important observation, which you all should noticed:

Delay between A and Y
Graph base analysis (Min, Max) : 7.25ns, 10.35ns
Path base analysis (Min, Max) : 7.55ns, 10.10ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA

Delay between B and Y
Graph base analysis (Min, Max) : 7.75ns, 10.85ns
Path base analysis (Min, Max) : 7.75ns, 10.30ns

You can see that delay between B and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA = min_delay_in_PBA
max_delay_in_GBA > max_delay_in_PBA


Delay between C and Y
Graph base analysis (Min, Max) : 7.05ns, 9.05ns
Path base analysis (Min, Max) : 7.25ns, 9.05ns

You can see that delay between A and Y - in case of GBA is superset of PBA.
Means:
min_delay_in_GBA < min_delay_in_PBA
max_delay_in_GBA = max_delay_in_PBA

Let me summarize whole concept:
min_delay_in_GBA <= min_delay_in_PBA
max_delay_in_GBA >= max_delay_in_PBA

Now, everything is good but still you may have confusion or question - why GBA? Because from above calculation, it's not clear how it's going to save Analysis Time of a Tool. How it's beneficial for Industry? If you have all these questions, no need to worry, I will explain but not in this article. I will do that next time. But I can give you hint, so that you can think about this once.
Hint:
1) Check how these minimum and maximum delays are calculated?
2) Adding Pessimism is not an problem, it's just margin in your delay calculation. How adding margin can help us?
3) What all different environment or other factors or parameters you have to consider while calculating Delay based on different timing Arc of a gate?

I think, for now, these hints are good enough. Comment here - if you know the Answer of this, else wait for next related article. :)


BEST OF LUCK.
By - Puneet Mittal
(Founder of VLSI-Expert Group)
PBA)


Monday, October 30, 2017

Technology File: Modelling of Dielectric Layer

Background of Types of Dielectric layer


Dielectric layers are of 2 types.
  1. Planar Dielectric
  2. Conformal Dielectric
Note: We have already discussed about the conformal dielectric in detail. You can review once again (Click here).

Below figures can help you to refresh your memories about Planar and Conformal dielectric.

Planar Dielectric:

All Dielectric in the below figure (D1 to D7) are Planar dielectric.


Conformal Dielectric:

Different type of Conformal dielectric structures are shown in below figure. There are certain parameters which helps to identify any conformal dielectric like Side thickness, Bottom thickness or Top thickness.


Modelling of Dielectric in Technology File


Modelling of Dielectric layer in technology file vary as per extraction software or you can say that as per EDA vendor. Different EDA vendor uses different ways to represents this as per their requirement. Even if I know their syntax, I can't write here. :) But what I am going to do - explain everything in more easy language. :) Once you start working, you can check their manual and try to map my syntax with their syntax. :)

To represent a Planar Dielectric (Non-Conformal) we need to have following basic information.

(Parameter Name : my_nomenclature )
Dielectric constant : di_constant
Thickness : thickness
Height from the Substrate : height
Name of Dielectric : DIELECTRIC
Type of Dielectric : conformal=false

To represent a Conformal Dielectric we need to have following extra information.

(Parameter Name : my_nomenclature )
Side Thickness : S_thickness
Bottom Thickness : B_thickness
Top Thickness : T_thickness
Type of Dielectric : conformal=true
Parent Layer : p_layer (This is the layer around which dielectric is present. It can be a conductor like Poly, Metal1 or may be any other Dielectric also. In above figure, M1 is the Parent layer).

Planar Dielectric


Modelling in Technology file:

DIELECTRIC DEL2
  di_constant = 4.8
  thickness = 2.7
  height = 4.1
  conformal = false

DIELECTRIC DEL3
  di_constant = 2.8
  thickness = 0.3
  height = 6.8
  conformal = false

Conformal Dielectric

There are different scenarios which need to understand. These scenarios are same as we have discussed in the article of Conformal Dielectric (It will help you to map easily)

Scenario 1:



Modelling in Technology file:

DIELECTRIC DEL_M1a
  conformal = true
  T_thickness = 0.2
  S_thickness = 0.2
  B_thickness = 0
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

DIELECTRIC DEL_M1b
  conformal = true
  T_thickness = 0
  S_thickness = 0.2
  B_thickness = 0.2
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

Scenario 2:



Modelling in Technology file:

DIELECTRIC DEL_a
  conformal = true
  T_thickness = 0.2
  S_thickness = 0
  B_thickness = 0
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

DIELECTRIC DEL_b
  conformal = true
  T_thickness = 0
  S_thickness = 0.2
  B_thickness = 0
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

DIELECTRIC DEL_c
  conformal = true
  T_thickness = 0
  S_thickness = 0
  B_thickness = 0.2
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

Scenario 3:



Representation of DEL_a1, DEL_a2 and DEL_a3 in Technology file:

DIELECTRIC DEL_a1
  conformal = true
  T_thickness = 0.2
  S_thickness = 0
  B_thickness = 0
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

DIELECTRIC DEL_a2
  conformal = true
  T_thickness = 0.15
  S_thickness = 0
  B_thickness = 0
  di_constant = 2.8
  thickness = 0
  height = 4.1
  p_layer = DEL_a1

DIELECTRIC DEL_a3
  conformal = true
  T_thickness = 0.15
  S_thickness = 0
  B_thickness = 0
  di_constant = 1.8
  thickness = 0
  height = 4.1
  p_layer = DEL_a2

Remember: In above representation, for DEL_a2, p_layer is previous dielectric (i.e DEL_a1). It's because this dielectric has parent layer DEL_a1. It's deposited on the top of DEL_a1. Top thickness also measured with respect to DEL_a1.
Note: you might be thinking why Height parameter is same in all 3 cases. It depends on EDA vendor, how they want to represent the height of Conformal layer. Here I am assuming that my tool is going to automatically measure actual height with the help of provided data. :)

Representation of DEL_b1 and DEL_b2 in Technology file:

DIELECTRIC DEL_b1
  conformal = true
  T_thickness = 0
  S_thickness = 0.2
  B_thickness = 0
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

DIELECTRIC DEL_b2
  conformal = true
  T_thickness = 0
  S_thickness = 0.15
  B_thickness = 0
  di_constant = 2.8
  thickness = 0
  height = 4.1
  p_layer = DEL_b1

Similarly, Representation of DEL_c1 and DEL_c2 in Technology file:

DIELECTRIC DEL_c1
  conformal = true
  T_thickness = 0
  S_thickness = 0
  B_thickness = 0.2
  di_constant = 3.8
  thickness = 0
  height = 4.1
  p_layer = M1

DIELECTRIC DEL_c2
  conformal = true
  T_thickness = 0
  S_thickness = 0
  B_thickness = 0.15
  di_constant = 2.8
  thickness = 0
  height = 4.1
  p_layer = DEL_c1

Scenario 4:



Modelling in Technology file:

DIELECTRIC DEL2
  conformal = true
T_thickness = 0.1
  S_thickness = 0.2
  B_thickness = 0.0
  di_constant = 2.8
thickness = 0.4
  height = 4.1
  p_layer = M1

DEL2 is a conformal dielectric & the reason behind this is - It has a Side Thickness and Top thickness parameter. But you may be thinking that it looks like a planar at all other places, it's shape is similar to non-conformal dielectric. I can understand your confusion. Actually, you are right that at certain places it's conformal and at some places it's non-conformal.
In the representation of all conformal layer, you may have noticed that thickness parameter is 0. It's because they dnt have any thickness as such (I am not talking about top thickness. That's a different parameter). In this case, this thickness parameter is non-zero like in case of Planar dielectric.

At the end, I just wanted to highlight once again that different EDA vendors have different syntax and different way to represent dielectric layers in technology file. Above representation is just for your understanding purpose, it's not specific to any company.

Friday, October 27, 2017

Metal Layer Stack (Nomenclature) Part 2

In the last part we have discussed about the Metal Stack. The way foundry provide data, different restrictions and available options. Now it's time to understand the very next step - how to communicate the complex Metal Stack information across the design team or groups or companies. For this Foundry also provide Nomenclature of metal stack.

If you remember in the last article we have discussed that there are different metal wires like Mx, My, Mz, Mr , Mu, etc (in XYZ Foundry). Below diagram can help you to remind this very well.


Now, lets suppose you want to use Stack type 7 and same you want to communicate to other user, then there is a standard way for this. (You might be thinking that I will communicate directly that you are referring Stack type 7. But if we do this - every time user has to refer this table to understand different metal layer optons. :) ).

If you will check closely the Stack Type 7, you will find below information.
  • There are Total 6 metal layers.
  • Metal 1 is of M1 type.
  • Metal 2, 3, 4 are of Mx type. Means next 3 Metal layers (After M1) are of Mx type.
  • Metal 5 is of My type. Means next 1 metal layer (after Mx) is of is of My type.
  • Metal 6 is of Mz type. Means next 1 metal layer (after My) is of is of Mz type.

Now, if I combine all this information and write something like this.

M1_3Mx_My_Mz : 1 (M1 Type) + 3 (Mx type) + 1 (My Type) + 1 (Mz Type) = 6 Metal layer.

Between 2 metal layers (e.g M1 and M2) - we will use VIA as per upper metal layer type (e.g Vx type)
The way I have defined the sequence also help to understand the sequence of Metal layer.

Any one can now interpret that :
Metal 1 = M1
Metal 2 = Mx1 (Mx Type)
Metal 3 = Mx2 (Mx Type)
Metal 4 = Mx3 (Mx Type)
Metal 5 = My1 (My Type)
Metal 6 = Mz1 (Mz Type)

VIA 1 = Vx1 (Vx type)
VIA 2 = Vx1 (Vx type)
VIA 3 = Vx1 (Vx type)
VIA 4 = Vx1 (Vy type)
VIA 5 = Vx1 (Vz type)
Remember, number of VIAs are always 1 less then the number of Metal layers. :)

Different companies uses different way to understand this. Like following are few examples.
  1. M1_3Mx_My_Mz : 1 (M1 Type) + 3 (Mx type) + 1 (My Type) + 1 (Mz Type) = 6 Metal layer.
  2. 3Mx_My_Mz : 1 (M1 Type) + 3 (Mx type) + 1 (My Type) + 1 (Mz Type) = 6 Metal layer.
  3. 3MxMyMz : 1 (M1 Type) + 3 (Mx type) + 1 (My Type) + 1 (Mz Type) = 6 Metal layer.
  4. 6M_3MxMyMz : 1 (M1 Type) + 3 (Mx type) + 1 (My Type) + 1 (Mz Type) = 6 Metal layer.
  5. 1P6M_3MxMyMz : 1 (M1 Type) + 3 (Mx type) + 1 (My Type) + 1 (Mz Type) = 6 Metal layer.

Note:
  • In the 2nd, 3rd, 4th and 5th option, First Metal layer M1 is considered by default.
  • In the 4th option, It was mentioned explicitly that stack has 6 metal layer (6M).
  • In the 5th option, It was mentioned explicitly that stack has 1 Poly layer (1P) and 6 metal layer (6M).

For the above figure, I have added all the nomenclature as per 5th option. Also for your easiness, I have mentioned Stack name at the Top and Bottom (both places same information). I am sure, after this there will be no confusion. :)


In the last, I just wanted to highlight that above nomenclature and metal stack options is for 1 foundry. But different Foundries may have different ways to provide and representation their information. With in the companies or group or team, they can also decide their own way to represent Metal Stack but when they communicate with outside world, either they have to use certain standard or they have to provide details of their nomenclature (which is very common).

Monday, October 23, 2017

Metal Layer Stack (Metallization Option) Part 1


There are different metal layers which we uses in our design. As we move down the technology node number of standard cells increases or you can say that number of connections increases drastically. As all of us know that these connection are made of Metal wire, it means number of metal wires increases. Below figure help you to understand the scenario.

Case1 : I didn't decrease the size of the chip (despite change in the no of standard cells per unit area) as we go down the technology node. You can see that number of metal wires increases. Silicon utilization improves with improved routability. But these numbers (standard cell) increases 4 times (per node if we are decreases the size by 1/2, overall area decreases by 1/2*1/2=1/4). With available options of metal wire in higher node, it's difficult to route the same design in lower technology node. And that's the reason as we go down number of metal wires increases (vertically also).

Case 2: This is the real scenario. As Technology node decreases, no of standard cells increases and also chip size decreases. So you can imagine how difficult it is to route the design with a single metal wire or say on a single level. That's the reason we have multiple levels of metal wires. These levels are in vertical direction. As we go down the technology node, these levels increases. So you can say that down the technology node, size of the chip decreases in one dimension (in 2D) but increases in other dimension (vertically). :) :)

Technology Node Vs Routing Complexity

To take care about the above options, foundry provides different option of metal in every technology node. These options are based on metal width, space, thickness or sometime other parameters. (You will get more clarity as we discuss more).

Type of Metal Wire


On the basis of Metal wire parameter or say property, foundry divide or say categorize different metals. These metal wire are named differently to distinguish from each other. Let's assume XYZ foundry have nomenclature of Mx, My, Mz, Mr. Different technology node will have different options. For example.

In Technology node X.

Mx:   First Inter-layer Metal:   Min_width = 0.1um & Min_space = 0.1um.
My:   Second Inter-layer Metal:   Min_width = 0.4um & min_space = 0.4um.

In Technology node Y.

Mx:   First Inter-layer Metal:   Min_width = 0.08um & Min_space = 0.08um.
My:   Second Inter-layer Metal:   Min_width = 0.18um & min_space = 0.18um.
Mz:   Top Metal layer:       Min_width = 0.4um & min_space = 0.4um
Mr:   Top Metal layer:       Min_width = 0.5um & min_space = 0.5um

In Technology node Z.

Mx:   First Inter-layer Metal:   Min_width = 0.05um & Min_space = 0.05um.
Mya:   Second Inter-layer Metal:   Min_width = 0.12um & min_space = 0.12um & thickness = 2800A
Myb:   Top metal layer:   Min_width = 0.12um & min_space = 0.12um & thickness = 3200A
Mz:   Top Metal layer:       Min_width = 0.4um & min_space = 0.4um
Mr:   Top Metal layer:       Min_width = 0.5um & min_space = 0.5um

Note: These min_width and min_spacing numbers are not related to any technology node. I just picked these randomly to help you to understand how different metal wires are categorized.

As we go down these available options increases. Like Mx, My, Mz, Mu, Mr, Mw and so on. For exact numbers of metal and their property plz refer foundry provided documents.

Foundry also recommend based on the uses of metal wire. Like few metal wire options with a relaxed pitch (minimum_width + minimum_spacing = Pitch) for power, clock, busses and other important signal distribution. Tighter pitched options for general signal routing. You can also see (In Technology Node Z) that Mya and Myb are also 2 different type of metal wire because their Thickness values are different (even though their min_width and min_spacing are same). So you can understand that as per the uses, foundry provides a lot of options. Now it's upto designer how to use those options.

Foundry provide this (above) information in several ways so that user can understand it very clearly. One thing I want to highlight here that user have flexibility to choose metal layers but out of available options. Stay tune to understand this point.

Cross-section diagram of a Metal Stack:


First try to understand below pic :)


This is basically a cross-section of different metal wire after the fabrication. In the sense, how different metals are placed and how they are connected. Sometime lot more details can be provided along with this pictorial view like min_width and min_spacing of every metal wire, name of the dielectric, thickness of metal wire and dielectric. It varies from foundry to foundry & process to process.

Another representation of cross-section of Metal Stack (Source: VLSI Research INC - Downloaded from Internet)


Here you can see, they have explained from real fabrication point of view and also explained what are different components of first metal film stack, second metal film stack and so-on as per their process.

Note: Above cross-section foundry can provide for maximum available Metal stack. Now if you are confused what is the meaning of "available" metal stack (refer below pic)

Tabular diagram of Metal Stack:


Basically it's metallization option available or say provided by the foundry. They can provide this in the table form to make things crystal clear. Cross-section diagram can help you but drawing the cross-section of each and every stack is not possible. So they created table something like this (below).

Note: I have only created a very small subset of actual table but it is sufficient to understand foundry data.


I have only captured 21 stack type. There can be more also. Now let's try to understand this table more closely.
  • For 3 Metal layer - there is only 1 option available. (Stack type 1)
  • For 4 Metal layer - there is only 1 option available. (Stack type 2)
  • For 5 Metal layer - there is only 2 option available. (Stack type 3,4)
  • For 6 Metal layer - there is only 3 option available. (Stack type 5,6,7)
  • For 7 Metal layer - there is only 6 option available. (Stack type 8-13)
  • For 8 Metal layer - there is only 8 option available. (Stack type 14-21)
  • There are no other available options for any metal layer stack apart from provided in the table. Like if you need any other combinations of metals for 5 metal layer, it's not available. (Restriction provided by foundry)
  • Metal layer "Mr" can not be used in case of 3, 4, 5 &6 metal layer stack. (Restriction provided by foundry)
  • Top Metal layer can be of either Mz or Mr (for metal stack more then 6). (Restriction provided by foundry)
  • My, Mx Layer can't be Top metal layer. These are always inter-layer metal. (Restriction provided by foundry)
  • M1 is always First metal layer. (Restriction provided by foundry)
  • Sequence of Metal layer is M1 -> Mx -> My -> Mz/Mr. You can't change the sequence. (Restriction provided by foundry)

Following information can supplement above diagram (also provided by foundry) and sometime easy to understand. If you can understand this properly, you can form any stack diagram or say you can understand all available options provided by foundry.


Similar type of table can be provided for VIA also.

Now from Foundry point of view, every things looks good. But you may be thinking
  • How this information is going to use in the design?
  • How are designers going to communicate with each other about a certain metal stack?
  • Is there any standard for communication point of view with in a Design Team?
You may have lot of other questions, Lets wait for second part of this article to understand more about the Metal Layer Stacking from Designer point of view.

Sunday, October 22, 2017

Physical Design Interview Questions (Part 2)


Second part of this series. There are few sets of questions which is very common from Physical Design Interview point of view.
One of my Student shared below questions with me and as I always do - Sharing with everyone. :) He told me that he got offer from 6 service based companies after practicing only these questions. I haven't validated his statement and going with his words. :)

Note: Not mentioning the Answer of these questions right now. But I will do that later on. If anyone of you can do this for me or others (in lesser time compare to my time)- that will be great. I will explain these Answers one by one in detail fashion, so obviously it will take time. :)

Third Set of questions (Asked in third Company)
Remember- first 2 set of questions already covered in previous article.
  1. What are the inputs given to PnR / What it contained?
  2. What are things will you do in data-setup?
  3. How will you place macros?
  4. Let A, B, C, D are four macro in a block, A & B are in same hierarchy and they are communicating with each other, D is also in same hierarchy as A & B but not communicating with A & B. C is in different hierarchy but communicating with D. How will you place the macros?
  5. What are the reason behind congestion between the macros?
  6. How will you find the spacing between two macros?
  7. How will you resolve congestion inside Standard cell?
  8. What is power planning?
  9. How will you reduce IR Drop?
  10. What is CTS? How will you synthesis clock tree and what are clock tree optimization?
  11. What is pre-routing?
  12. What are the low power techniques we used for the submicron technology?
  13. In a timing check between 2 FF, hold slack is +2ns but setup is failed by -10ns. How will you resolve it?

These are few set of questions which has been asked in 3 companies (2 sets, I have already shared in previous article). I am sure - lots more can be asked. My intension to captured these questions at this place is not to provide a list of questions which can 100% help you to crack any interview but I want to show you a pattern of questions and the amount of preparation which you need to do.
Like I said in my previous article - "I am not saying that only these questions are sufficient for you to crack any PD (Physical Design) Interview, but I am 100% sure that these will help you to understand if your preparation is good enough and also provide you certain direction in your preparation."

Just wanted to share one incidence before I finish this article.
After my first article, one of my friend from VLSI Industry (working as senior PD manager) called me and asked if I am doing the right thing to captured all these questions.

His concern was - what if candidates don't have understanding about whole PD flow but they know (mug-up or remember) all these questions and answer all of them correctly. They can't survive in Industry for Long, so am I doing justification with them? :)

In reply of this - I just asked one question to him - Are you asking same set of questions everytime in a same sequence & wording? He got my message and I hope same with you all.

In case, you need my help to check whether you are ready for Interview or NOT, Please request for the MOCK Interview. We can connect and you are going to treat as Interviewee. After the MOCK interview, I will provide you detailed feedback.
Steps to request for MOCK Interview Sessions are below.
  1. Fill all details of this Form.
    Registration Form
  2. WhatsApp your NAME and Location at 9740033323.
  3. Book your 30min Slot
  4. After the Mock Interview - Get Detailed Feedback at your Mail id

BEST OF LUCK.

Sunday, October 8, 2017

Physical Design Interview Questions (Part 1)


There are few sets of questions which is very common from Physical Design Interview point of view.
One of my Student shared below questions with me and as I always do - Sharing with everyone. :)

Note: Not mentioning the Answer of these questions right now. But I will do that later on. If anyone of you can do this for me or others (in lesser time compare to my time)- that will be great. I will explain these Answers one by one in detail fashion, so obviously it will take time. :)

First Set of Questions (Asked in One Company)
  1. Draw APR Flow
  2. When we will place "Physical Only Cells"
  3. What are "Spare Cells" and why it is used?
  4. Why do you make clock as Ideal during floorplan & Placement Stage?
  5. What are the different Checks we do in the CTS stage?
  6. What if Setup is failed after manufacturing of chip?
  7. How will you fix Hold?
  8. What is the Importance of useful Skew?
  9. What are DRV Checks and why do we check that?
  10. What is the cross talk? How it will effect the performance?
  11. Cross delay or Cross talk noise is note generally. Why?
  12. A Blocks having 7 Metal layers and same block having 10 metal layer, which will function better and why?
  13. How will you define the shape of the Die?

Other set of questions (Asked in Second Company)
  1. Draw and Explain APR flow.
  2. How will you place Macro?
  3. How will you reduce congestion near I/O parts?
  4. Where will you implement partial blockage?
  5. What are checks you will do after each stage of PNR?
  6. What is Setup and Hold Time?
  7. Few problem based on Setup and Hold Calculation.
  8. What are the Timing check will you do apart from setup and hold check?
  9. What if Setup and Hold Both fails?
  10. How will you resolve Setup and Hold Issues?
  11. What are clock free targets and buffer constraints?
  12. How will you fix DRV?
  13. How will you do cloning?
  14. Which metal will you use for Power routing and Why?
  15. What are routing grids?
  16. What is Antenna Effect and how will you resolve it?
  17. What is Antenna Ratio?
  18. What is Latch up and How will you resolve it?
  19. How will you place TAP Cells and in which Stage will you place Tap cells?
  20. Why ENDCAP Cells are used ?
  21. What all Datas will be given to FAB after Tapout?
  22. Why Derates are used for Timing Calculation? Is it Good or Bad?

I was thinking to list down Companies name here but then realized what if they stop asking these questions. :) :) But Point is these questions are very much related to concepts of whole PD flow. I am not saying that only these questions are sufficient for you to crack any PD (Physical Design) Interview, but I am 100% sure that these will help you to understand if your preparation is good enough and provide you certain direction in your preparation.

In case, you need my help to check whether you are ready for Interview or NOT, Please request for the MOCK Interview. We can connect and you are going to treat as Interviewee. After the MOCK interview, I will provide you detailed feedback.
Steps to request for MOCK Interview Sessions are below.
  1. Fill all details of this Form.
    Registration Form
  2. WhatsApp your NAME and Location at 9740033323.
  3. Book your 30min Slot
  4. After the Mock Interview - Get Detailed Feedback at your Mail id

BEST OF LUCK.


Monday, October 2, 2017

Delay Interview Question (Part1)


Let's discuss the Delay concepts from Interview point of view. Several times it happen that Interviewer is going to ask certain questions and the moment you answer it - they will change the case or scenario without changing the Diagram or values. Few of the scenarios, I am going to discussing here. Remember - As a Interviewer - our intension is to check "how much you know" and "How much you can visualize from Tool perspective or real design point of view".

Example 1:



All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay = (1.25ns, 1.5ns)
OR gate (min, max) delay = (0.3ns, 0.4ns)

Note: These min and max delay numbers are not corresponding to rise and fall delay number.

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
This question is very easy. You have to understand only 1 thing, There are 2 paths and question is all about min and max delay between Q1 and D2.So, you have to calculate both min and max delay with respect to both the paths and then figure out which one is minimum or maximum out of 4 delay values.

Solution:
Path 1 (Min Delay) : 0.25 + 1.25 + 0.1 + 0.3 + 0.1 = 2ns
Path 1 (Max Delay) : 1.0 + 1.5 + 0.2 + 0.4 + 0.2 = 3.3ns

Path 2 (Min Delay) : 0.25 + 0.25 + 0.25 + 0.3 + 0.1 = 1.15 ns
Path 2 (Max Delay) : 1.0 + 1.0 + 1.0 + 0.4 + 0.2 = 3.6 ns

Overall Min Delay between Q1 and D2 = 1.15ns (From Path 2)
Overall Max Delay between Q1 and D2 = 3.6ns (From Path 2)


Example 2:



All Buffer has same (min, max) delay = (0.1ns, 0.2ns)
All NOT Gate has same (min, max) delay = (0.25ns, 1ns)
AND gate (min, max) delay = (1.25ns, 1.5ns)
OR gate (min, max) delay = (0.3ns, 0.4ns)

Note: These min and max delay numbers are corresponding to rise and fall delay number respectively.

Question: Find out the Minimum and Maximum Delay between Q1 and D2?

Explanation:
Now this question become tricky. As per Note - I have mentioned that these min and max delays are actually rise and fall delay. If this is the scenario, we have to understand circuit and find out more accurate Min and Max delay between Q1 and D2. Remember, above numbers (Min and Max delay in Example 1) is also correct but we are talking about more accurate number. This is the only trick or say the intension of Interviewer to ask you this question with slightly change in wordings. :)

We have to do 2 type of analysis for each path - Rising & Falling signal analysis at D1 for both paths.

Rising Signal Analysis (For Path1):
  • Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • AND gate is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for AND gate => 1.5ns
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
  • OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for OR gate => 0.4ns
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 1 + 1.5 + 0.2 + 0.4 + 0.2 = 3.3ns

Falling Signal Analysis (For Path1):
  • Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • AND gate is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for AND gate => 1.25ns
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
  • OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for OR gate => 0.3ns
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 0.25 + 1.25 + 0.1 + 0.3 + 0.1 = 2.0ns

Rising Signal Analysis (For Path2):
  • Inverter is Negative Unate -> Rising Signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • OR is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for OR gate => 0.4ns
  • Buffer is Positive Unate -> Falling signal at input means falling signal at output -> Means Fall delay is going to be consider for Buffer gate => 0.2ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 1 + 0.25 + 1 + 0.4 + 0.2 = 2.85ns

Falling Signal Analysis (For Path2):
  • Inverter is Negative Unate -> Falling Signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • Inverter is Negative Unate -> Rising signal at input means falling signal at output -> Means Fall delay is going to be consider for NOT gate => 1ns
  • Inverter is Negative Unate -> Falling signal at input means rising signal at output -> Means Rise delay is going to be consider for NOT gate => 0.25ns
  • OR is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for OR gate => 0.3ns
  • Buffer is Positive Unate -> Rising signal at input means rising signal at output -> Means Rise delay is going to be consider for Buffer gate => 0.1ns
So, overall for Path 1: For Rising Signal Analysis -> Delay = 0.25 + 1.0 + 0.25 + 0.3 + 0.1 = 1.9ns

Solution:
Path 1 (Min Delay) : 2ns (Because of Falling Signal Analysis)
Path 1 (Max Delay) : 3.3ns (Because of Rise Signal Analysis)

Path 2 (Min Delay) : 1.9ns (Because of Falling Signal Analysis)
Path 2 (Max Delay) : 2.85ns (Because of Rise Signal Analysis)

Overall Min Delay between Q1 and D2 = 1.9ns (From Path 2 - Falling Signal Analysis)
Overall Max Delay between Q1 and D2 = 3.3ns (From Path 1 - Rise Signal Analysis)



Do you think that's all .. NO NO NO .. Still there are couple of scenario which can be asked using same figure. Always remember - Interviewer never stop like this. :) :) Check Next Article of this series, where we are discussing about Arc based Delay calculation along with High to Low & Low to high Propagation Delay.

Monday, September 18, 2017

Mantra For Success: Open to gain new knowledge (True Story of VLSI Aspirant)


After a long time, I came across to one of my student who compromised a lot, struggled a lot but finally learned a lot. His attitude of learning new concepts, believe in himself and his fighting sprit against odd scenarios - helped him to open doors of success.

I requested him to share his story and he did a awesome job.
I wish him BEST of LUCK for his future.

EVERYONE Should read HIS Story once (Whether you are VLSI aspirant or not - it doesn't matter). It will motivate you a lot.


My journey to get a job in ASIC RTL Design

After completing my masters from one of the most reputed universities in western Europe, I thought that when I get back to India, getting a job will be cake walk. There were some reasons why I couldn't stay back in Europe. I was highly excited to come back to India. My energy levels were all time high and I was very optimistic. Only to later realize that I stepped onto a road full of thorns.

It was December of 2015, I landed in Delhi, breathed with relief that I got back to my country. I was happy to begin a new journey of life. Everyone at home was very happy. After a short vacation, I started to look for a job. My days were fully consumed in job applications. Uncountable mails, relentless search on job portals , phone calls and LinkedIn search became a way of like for the next three months. Parents had high expectations, though they never expressed directly to me, but their eyes spoke of everything.

As days passed, my anxiety increased only to further invite health issues. In all these days, I gained about 15 kg of weight only to become obese. That was not enough, I started suffering from insomnia. Being unable to sleep for nights, I was unable to do any work in the morning, to become further lazy. I can remember an incident of one night, it was 4 o'clock, everyone was sound asleep at home except for me. Being unable to sleep, I started walking in the dining area and a sudden frustration wrecked into my mind. I started banging my head against the wall and started crying out loudly. Everyone woke up in a shock to see my state. I think, that day my parents realized that I need some help and some immediate attention. The next few days, I focused on improving my health and went for therapy to cure insomnia. I started working out. I saw good results. I was better than before. Later I decided that I will leave for Bangalore.

It was mid of March 2016 when I joined a known institute in Bangalore to get trained in RTL Design and Verification. The institute promised a 100% job assistance. I was happy that I have moved on. The next four months were consumed in the training. Though I did not typically required such a training, but getting a job was my hope. In my training days, I realized that my only interest is in RTL Design and not RTL verification. People suggested to me that I should first enter the industry and then have such strict criteria. But I did not budge. After four months of training, I started my job applications on my own as the training institute was not able to get a Design position.

I was living alone in a one room and a kitchen apartment in Bangalore. During the training, I did not realize my loneliness, but as it ended, I realized how alone I am. I used to study for all of day, also applying to positions. Initially I got some interview calls, but they went unsuccessful. Later I stopped receiving any further interview calls. No replies from HRs added further to my anxiety. I started contacting people on LinkedIn, but rarely would anyone reply. Expecting any reply from HRs was anyways hopeless.

But somehow god gave me strength to keep moving. I utilized my time to polish my skills. I solved Charles Roth completely, and other books as well. Even though I was working very hard, at nights while going to bed I used to feel sheer nervousness. My hands would shiver out of fear and nervousness. Seven months had passed and I was still jobless. Then a friend called me and said that I should start focusing on Verification and start revising SV, UVM etc. because getting a job in Verification is easier. I thought that it is the right way to go forward and I started doing it, loosing all hopes that I will get a job in RTL Design. It was third week of February of 2017 that I got a call from a service based company in NCR that they want to schedule an interview for RTL Design position with me. My happiness knew no bounds because it was my first interview after a couple of months. I gave the interview and I got selected!

I cannot express how happy everyone was. I couldn't believe that I made it. I soon joined that company. I met new people and made new friends. It was there where I realized that why my CV was not being shortlisted. I also lacked knowledge in STA. I got to know how to prepare CV for RTL Design position. I made mistakes, my approach was wrong, but my hard work paid off.

I got the chance to get lectures from Puneet sir on STA in Noida. Those lectures made me an expert in STA analysis. I was working very hard in the company as well, polishing all my skills and upgrading them. I learnt to operate Cadence tools. It significantly improved my profile. After six months in that company, I got selected in a very well known semiconductor company in Bangalore. I have just completed my first week in my new company. Now almost everyday I am getting a call from some company. Life seems so good now! I am fit, healthy and I sleep very sound. I am happier. Thanks to god, parents, friends and Puneet sir. I have made it.

I just want to say that never ever loose hopes. Stay strong and stay focused. Making friends is very important than anything else. Strong belief in god will help too. If you are not getting results,
  1. Please analyze where you are going wrong,
    • is it your approach ?
    • Or is it your level of knowledge that needs to be upgraded ?
  2. Always be open to any opportunity on the way even if it is low paying, because one door provides a gateway to a new world.
  3. Never think twice in gaining new knowledge. Go for as many workshops in your domain as possible.
  4. Talk to people if you are getting confused.
  5. And at last, be confident.

I have requested Puneet sir to keep my profile anonymous. But if you want some help from me, talk to Puneet sir, he will give you my contact details or message me on my mail id: rtldesignexpert@gmail.com. I would like to help anyone who is struggling to get a job in the semiconductor industry.

Thank you.

Once again - Best of Luck - A**k. :) Be in touch and ping me any time if you need my help.

Wednesday, April 12, 2017

Proper Assessment With detailed Feedback is missing for VLSI Candidates !


This article is mainly for VLSI aspirants, Evaluators or Developers (Assessment developer). "Assessment with detailed Feedback" is an indispensable factor missing in Education system related to Semiconductor/VLSI Industry. Assessment happens at every stage and everyone provide some type of feedback but effectiveness of both of these for VLSI industry is a topic of discussion here.

I try to highlight a common career path of a candidate before getting into job (it will help you to understand my point).

  1. Admission in XYZ Engineering college
  2. Scoring marks in different subjects like Digital electronics, VLSI Design, Microprocessor, Analog electronics, Semiconductor Theory and others
    • Remember: These scores or Marks are based on general or say all topics (not specific to any Industry)
  3. Campus Selection process.
    • Remember: In most colleges, either core companies (specially Semiconductor) don't visit or candidates don't able to meet selection criteria.
  4. If, not able to select or crack any VLSI Company interview, start thinking about other options.
  5. Other options are
    • Mtech (another 2 Year)
    • Training Institute (another 1 year and almost Rs 1Lakh)
  6. If, Opt for Mtech
    • Same process (as for Bachelor Degree: Step 2 to 4)
    • Even after Mtech, Most of the candidates again stuck at Step 4
    • Most of the Time, they opt for Training Institute.
  7. In case of Training Institute
    • Spend 1 more year
    • Spend money between Rs 50k to Rs 3lakh
    • Training Institute sometime offers you a job with a 3 year bond.

Assessment


Now it's time to understand what are different types and numbers of assessments in above career path. After that, we will discuss feedback mechanism.

Assessment Type:
  • B.Tech/B.E. External assessment:
    • Also known as Semester exam.
    • Structured to pass maximum students.
    • These assessments or say Exams are not based on any Industry.
    • These are common for all Industry.
  • B.Tech/B.E Internal assessment:
    • Also known as sessional or Internal exams
    • Specific to a particular topic but prime focus is to prepare students for Semesters.
    • Again, these are common for all industry
  • Entrance Exam (Competitive Exams):
    • Either for Mtech like GATE or for Training Institute.
    • Based on the maximum rejection. In general, Lakhs of students apply for such entrance exams and seats are limited. So maximum rejection is the criteria.
    • Again there are not specific to any Industry (even though people claim this)
  • M.Tech or M.E level assessment: Same as in case of B.Tech/B.E.(Maximum students should pass; No specific Industry oriented assessment)
  • Assessment during Training Program:
    • This is the one place, I can say it's specific to concepts and as per requirement. But nowadays it's also changing it's face.
    • Institutes promised for Job assistance or sometime 100% placement to various candidates. They can't place everyone because of N number of reasons, so they have to increase the level of assessment (difficulty wise) compare to Industry requirement. It helps them in screening candidates.
    • Institutes focuses on the practical aspect, so their assessment is also based as per that. They can't assess students for fundamentals and basics.

What's Missing here? Everyone know about these assessment technique. :) If you try to look more closely, you will find ...

  1. Not a single assessment is Industry Oriented.
  2. There are different purpose for each assessment, either rejection or selection or screening candidates.
  3. Based on these assessment techniques, no one can/should claim that "I am Industry Ready".


Now the point is "How to develop Industry Oriented Assessment". As per my understanding, assessment should have following features. In case, it's not fulfilling, assessment become general and can't claim it as Industry oriented.

  1. Industry requirement based:
    • Understand the Industry requirement
    • Understand each and every profile
    • Develop the assessment as per requirement and profile
    • Should not target 2 or more Industries at a time
    • It will be good, if it's developed by Industry person or thoroughly reviewed by them
  2. Coverage should be 100%:
    • Should cover all required topics and concepts.
    • Every concept is going to be used one day or other. Before applying for a job, candidates should know their strong area. Same goes to hiring person also. They should also know the weak and strong area of a candidate.
    • No need to add unnecessary topics or concepts as a part of assessment (just to increase the length of assessment)
  3. Properly Linked with Feedback mechanism
    • Assessment should be linked with feedback mechanism.
    • If we want to improve the performance of a candidate through assessment, then assessment should be thorough and well planned. It should be very well documented and divided into sections, subsections and if required deeper level of hierarchy.
    • Should have all level of questions (easy to difficult). Remember ...
      • In the case of only difficult questions, assessment turns into rejection-based-assessment.
      • In the case of only easy questions, assessment turns into passing-based-assessment.
    • If we want to select or reject based on assessment, it should be as per Industry requirement in terms of skill sets, concepts, knowledge or even level of questions.
      • Industry always want to know strength of a candidate, so that they can utilize their strengths for productive work.
      • Industry is also interested to know weakness of a candidate, so that they don't plug him/her in wrong project.
      • Remember, Industry never select based on Strength or reject based on Weakness. They select or reject based on match/mismatch of requirements Vs strengths.

Feedback


Feedback Mechanism:
  • After B.Tech/B.E External assessment:
    • Final Score (e.g B Grade or 75% Marks)
  • After B.Tech/B.E Internal assessment:
    • Score along with some remarks from Lecturer or Professor
  • Entrance Exam:
    • The only percentile or say merit list (comparative report)
  • During M.Tech/M.E:
    • Final Score (e.g B Grade or 75% Marks)
  • During Training Program:
    • Score along with remarks from Trainer or Certificate in the end

Nothing is unknown to anyone. If you see closely, few of these are not even in the category of feedback. They are part of evaluation system. But I am highlighting these as a part of feedback because there is no other system in our education (or say career path) apart of these few. You may not be able to understand my point. :) Let me first highlight the features of Ideal Feedback mechanism.

  • Detailed and Appropriate.
    • It should highlight the strength and weak area of candidate. (Just highlighting good and bad with the help of score is not a feedback)
    • General remarks and specific remarks are two different things.
    • It should be detailed enough to appropriately highlight all gaps.
  • What next?
    • Feedback should be in such a way that it give direction for Next step.
    • If I am not sure how to use this feedback, there is no point of such feedback.
  • Should be fast enough (Instant feedback is best). If you are getting feedback after few weeks or so, it loses impact.

When we are talking about VLSI Industry, instant, proper, specific feedback lacks bigtime. Think about a scenario where you get detailed feedback about your performance and also get a chance to improve on your weak areas. That will help big time before you claim to be Industry Ready.


Above figure explain about the effort Vs score in different feedback mechanism. This can help you to understand what I am talking about. If feedback is instant and to-the-point, there are chances that I can improve on my weak areas in runtime(less time). But if it takes time, I have to spend more effort, energy, time to work on provided feedback.

Let me share few figures/charts for detailed and appropriate feedback. I will also explain how to interpret these.


Feedback Type 1: Topic Wise Performance Chart
  • It helps you to identify how good you are in a particular topic.
  • Total questions Vs Correct Vs Wrong, all information is present in a single chart.
  • It will also help you to identify your weak concepts.
    • E.g. Designing a "Latch using Mux" Vs "Flip-flop using Mux" Vs "Circuit realization using MUX". All are related to MUX but these are different concepts.
    • If, I provide a feedback that "your MUX is not good", you have to study complete MUX from scratch.
    • but if, I highlight the statistic in above fashion, it helps you big time to focus on a particular concept within MUX.
  • It helps you to understand pre-requisite of VLSI Industry.
    • You may not give importance to "Flip-flop using MUX" but after such feedback you can realize the importance of this concept.
    • Also helps you in terms of weightage of different concepts from VLSI industry point of view.


Feedback Type 2: Section wise Performance Analysis
  • It helps you to identify how good you are in a particular section.
  • These sections help to identify the Job profile.
    • Like If your Timing concepts are good, you should choose STA profile.
    • Not performing in Analog Section, means not recommended for Analog Design profile.
    • If Programming skills are not good, avoid Frontend side
  • So, these section's statistic helps you to identify your focus area. And sometimes can recommend your career path also.
  • In this Analysis, there are 3 areas (Total questions, question attempted and correct answer).
    • You have attempted some questions - that means as per your understanding those are your strong areas.
    • But such analysis points out that something is missing in those areas also. It may be because of some silly mistakes, over confidence, lack of fundamental knowledge or something else.
  • Such report helps to understand the weightage of different sections in VLSI industry.
    • Helps in time management during revision.
    • Helps to identify the effort level for a particular section.


Feedback Type 3: Overall performance
  • It helps "how good you are in general".
  • It's equivalent to final score (41/100) but mentally it's impact is different.
  • If any employer see this report, they have the opportunity to see "how much is the correct % out of attempted one". :)
  • Sometime such report works as a mirror. There are possibilities that you are running behind something which is not your cup of Tea.:)


Feedback Type 4: Average Statistic
  • It helps a user to understand "how good or bad he/she is compared to other candidates".
  • 56% unattempted and if you are also in that category, means you are not unique. :). If, you learn these topic or concepts, you can be one step ahead of others.
  • Only 19% are able to solve correctly. If you are one of them, means you are on the right track.
  • Such data helps a candidate to know their current level of preparation compared to others.
  • It can also help you to visualize where you stand compare to others.

Proper Assessment & Detailed Feedback


I am sure, by now you are good and understand the Ideal Assessment and Feedback mechanism.

It's time to understand how we can integrate Assessment and Feedback in a very effective way.

Feedback and assessment both are interlinked. If we know what type of feedback analysis we have to do and of what level, only then we can prepare/develop a proper and effective Assessment. Let me summarize this article with some pointer which also answers our initial question What is "Proper Assessment with Detailed Feedback"?
  • For highlighting correct weightage of different topic/sections in VLSI field (using feedback mechanism), assessment can't have unnecessary questions.
    • Assessor or developer should have thorough knowledge about the VLSI Industry. Preference goes to Industry experts or someone who already worked in the Industry for several years.
    • Assessor or developer should know what are the perquisites of a specific profile of VLSI Industry.
    • Assessor or developer should have good understanding of different sections, subsections, topics, concepts. It's not just randomly select few questions related to different sections/topics.
  • Level of question should be as per Industry Standard
    • Assessment is not for rejecting candidates for XYZ factor. Assessment should aim to screen the right skilled candidate.
    • Difficult level should not be above the standard because it may filter out right candidates.
    • Difficult level should not be below the standard because it adds one more level of screening process.
  • Assessment and Feedback both should help candidates for improvement
    • Assessment for screening or filtering candidates are almost without any feedback
    • Assessment should be designed to first highlight improvement area and it's only possible with detailed feedback.
    • Feedback should be in such a way that "What Next" is clear. For that assessment should be designed in a very different way.

In the last, just wanted to add one thing... VLSI students are not able to understand the importance of assessment today, they think training and courses are sufficient for them to get a job. But Remember, if you don't know where you stand and how much you are capable, you can't get success in your life.

Courage is not the absence of fear, but rather the assessment that something else is more important that fear.

Franklin D Roosevelt

The newly launched product "VLSI Self Mentorship Program" by Edusaksham, can help you in assessment along with detailed Feedback. Do free login and try sample papers to know more.

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