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Monday, March 28, 2011

"Time Borrowing" : Static Timing Analysis (STA) basic (Part 2)

STA & SI:: Chapter 2: Static Timing Analysis
2.1 2.2 2.3a 2.3b 2.3c 2.4a
Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b
Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2
2.6c 2.7a 2.7b 2.7c 2.8
Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

In a ASIC there are majorly two types of component. Flip-flop and other is Latches. Basically Here we will discuss about Latched based timing analysis.
Before this we should understand the basic differences between the latch based design and flip-flop based design.
  • Edge-triggered flip-flops change states at the clock edges, whereas latches change states as long as the clock pin is enabled.
  • The delay of a combinational logic path of a design using edge-triggered flip-flops cannot be longer than the clock period except for those specified as false paths and multiple-cycle paths. So the performance of a circuit is limited by the longest path of a design.
  • In latch based design longer combinational path can be compensated by shorter path delays in the sebsequent logic stages.So for higher performance circuits deisgner are turning to latched based design.
Its true that in the latched based design its difficult to control the timing because of multi-phase clockes used and the lack of "hard" clock edges at which events must occur.

The technique of borrowing time from the shorter paths of the subsequent logic stages to the longer path is called time borrowing or cycle stealing.

Lets talk about this. Please See the following figure.

Example of Latched based design.

There are 4 latches (positive level sensitive). L1 and L3 are controlled by PH1 and L2 and L4 are controlled by PH2. G1, G2, G3 and G4 are combinational logic paths. For now assume a library setup time is zero for the latches and zero delay in latch data-path in the transparent mode.
Now if assume that if  designs using edge-triggered flip-flops, the clock period has to be at least 8 ns because the longest path in G1 is 8 ns. Now as the clock pulse is 5ns , there is a voilation at L2. On the other hand, if the design uses latches , L2 latch is transparent for another 5ns and since the eighth (8th) ns is within the enabled period of L2, the signal along path1 can pass through L2  and continue on path2. Since the delay along path2 is 2 ns, which is short enough to compensate for the overdue delay of path1, this design will work properly. In other word we can say that path1 can borrow sometime (3ns) from the path2. Since the sum of path1 and path2 is 10ns, which is the required time of L3, there will be no voilation in either of the Latches. 
For the same reason, path3 can borrow some time (1ns) from path4 without any timing violation.

Note: A latch-based design completes the execution of the four logic stages in 20 ns, whereas an edge-triggered based design needs 32 ns.

Lets see this in a more complex design. Its self explanatory.
Example Of Timing Borrowing
Just wanted to convey here that this Timing borrowing can be multistage. Means we can easily say that for a latched based design,  each executing path must start at a time when its driving latch is enabled, and end at a time when its driven latch is enabled.

Few Important things:
  • Time borrowing occur with in the same cycle. Means launching and capturing latches be using the same phase of the same clock. when the clocks of the launching and capturing latches are out of phase, time borrowing is not to happen. Usually it was disabled by EDA tools.

  • Time borrowing typically only affects setup slack calculation since time borrowing slows data arrival times. Since hold time slack calculation uses fastest data, time-borrowing typically does not affect hold slack calculation.

Few Important terminology:

Maximum Borrow time: 
Maximum Borrow time is the clock pulse width minus the library setup time of the latch. Usually to calculate the maximum allowable borrow time, start with clock pulse width and then substract clock latency , clock reconvergence pessimism removal , library setup time of the endpoint latch.

Negative Borrow time:
If the arrival time minus the clock edge is a negative number, the amount of time borrowing is negative ( in other way you can say that no borrowing). This amount is know as Negative Borrow time.

Friday, March 18, 2011

How To Read SDF (Standard Delay Format) - Part3


In the Part2, we have discussed following things.
  • What are SDF Constructs?
  • Syntax of SDF file
  • Sample SDF file.
  • Header Section and details of various Constructs present in that.
As we come to know that SDF file has 2 different section. Header section ( which we have discussed in Part2 ) and Cell Section. He we will discuss about the Cell section.

Cell Section:

Cell Section has all the important information require for timing calculation like delay, timing constraints, timing environment and etc for a particular cell or part of the design.
In the SDF, its necessary that at least "1" (one) cell section should be present. There is no limit on higher side. Sequence of Cell section is also important in the SDF file. Lets suppose that there are 2 cell sections defining the timing properties/specification for same part of the design, then the information in one section can override (Replace the existing information- this will happen when the ABSOLUTE keyword is present in the cell section) Or may be cumulative with other information ( added to previous information- if INCREMENTAL keyword is present in the cell section). EDA tools read the file from top to bottom ( or say beginning to end) and apply the different constraint or information in the similar sequence.
So there are 2 files and both has overlap information then designer should take care of the sequence before sourcing those file in the EDA tool. 

Syntax of Cell section:      (CELL  <cell_type>  <cell_instance>  <timing_spec> )

Below are the different SDF file Constructs and their details which are the parts of Cell Section.

Fields/Entities of Cell Section
SDF File Constructs
Cell type
Name of a particular cell or a region of the design.
Cell instance
Specify the path of cell instance
Timing Specification
Specify the delay related information for back-annotation
Timing Check
Specify Timing checks limit data   for back-annotation
Timing environment
Specify timing environment data and constraint data for forward-annotation
Set the values of timing model variables upon that delays and timing constraint values depend

A snapshot of sample SDF file present in the part2 to understand most of the things.

(CELL                                                                             // Cell 2
(INSTANCE top/b/d)
(IOPATH a y (1.5:2.5:3.4) (2.5:3.6:4.7))
(IOPATH b y (1.4:2.3:3.2) (2.3:3.4:4.3))

(CELL                                                                              // Cell 3
(INSTANCE top/b/c)
(IOPATH (posedge clk) q (2:3:4) (5:6:7))
(PORT clr (2:3:4) (5:6:7))
(SETUPHOLD d (posedge clk) (3:4:5) (-1:-1:-1))
(WIDTH clk (4.4:7.5:11.3))
You can see that there are multiple definition of the Cell section. In each cell section, CELLTYPE and INSTANCE (cell_instance)  and at least one of the timing specification entity (DELAY, TIMINGCHECK, TIMINGENV, LABEL) is defined. There may be Zero "0" entity of timing specification in a particular SDF, but then there is no meaning of define that cell section.

Few more detail about above parameters...

It represent the Name of the Cell in the design. That may be either the cell name mentioned with in the Library (e.g standard cell library) OR name of a particular region with in the design ( e.g Name of a Block).
E.g- In my sample SDF file in part2, there are 3 types of CELLTYPE.
  • (CELLTYPE "MYDESIGN")  >> Name of My design.
  • (CELLTYPE "AND")  >> Name of a cell present in standard cell library.
  • (CELLTYPE "DFF")   >> Name of a block present in my design at some hierarchy.
It identify the region with in the design for which timing information is present in the cell section. If you want to apply the timing constraints for a particular instance of a cell, then you have to mention of the complete path of that particular instance. Else if you want to use associated timing data with all occurrences of the specified cell type, then in the INSTANCE mention wild character ( * ).
Path of the instance should start from the same level of design from where EDA tool (or say annotator) is instructed to apply the SDF file.
For example-
  • From the top level the path of AND gate is "Top/block1/block2/block3/AND" but you have instructed to annotator to apply a SDF from block2 level, then the path in the INSTANCE should be "block3/AND".
  • Similarly if you will mention (INSTANCE *) in the above case, then the timing information only link to the AND gate present in the same level or in below levels, not at a level of block1.
This entry should be in consistance with the CELLTYPE. It should not be the case that Cell name is AND and the instance path is with respect to the NAND gate.

Timing Specification:
Each cell in the SDF file shall include zero or more timing specifications that contain the actual timing data associated with that cell. There are four types of timing specifications that are identified by the DELAY, TIMINGCHECK, TIMINGENV, and LABEL keywords. Out of these DELAY and TIMNGCHECK data used for back-annotation and TIMINGENV used for forward-annotation. We will discuss about the back forward annotation in other blog.

Lets discuss these timing specification one by one.

There are 4 ways to implement the delay value on the design defined in the SDF file.
Types of Delay
SDF File Constructs
Path-pulse delay
Both Constructs specify how pulses shall propagate across paths in corresponding cell
Path-pulse percent delay
Absolute delay
Containing delay values to be applied to the region identified by the cell
Increment delay

Path-Pulse Delay and Path-Pulse Percent Delay:
As such both are same and only difference in terms of representation of value. In Path pulse Percent Delay every thing is in terms of percentage only.
These parameter usually apply a limit on a PULSE and determine whether a pulse of certain width can travel through a device or not and appear in which form to output.
Syntax is (PATHPULSE <input port> <output_port> <pulse_rejection_limit> <X-limit>)
  • If input_port and output_port is not defined then these limits applied to all paths present in the instance defined by cell entry.
  • pulse_rejection_limit means if the width of Pulse is less then this value, nothing will appear at the output.
  • X-limit means if width is less then this but greater then pulse_rejection_limit, output will be unknown (means X stage).
  • If any one value is provided in place of these 2 limits, then both limits are set to that value.
  • These Limits must not be in negative.
ABSOLUTE - introduce delay data to replace existing delay values in the design during annotation.
INCREMENT -introduce delay data that is added to existing delay values in the design during annotation.
Both of these can be specified with the help of same type of SDF constructs. These are based on the type of Delay in a design.

Delay type
SDF Construct
Input output path delay
Represent delays from an input/bidirectional port to an output/bidirectional port of a device.
Conditional Delay
Specify conditional (state-dependent) input-to-output path delays
Specify default delays (if none of the conditions specified for the path in the model is TRUE but a signal must still be propagated over the path) for conditional paths.
Port Delay
Specify interconnect delays (actual or estimated). Start point of the delay path is not specified.
Propagation/ Interconnect/ Net Delay
Specify the propagation delay across a net connecting a driving module port (the source) to a driven module port (the load).
Specify the propagation delays from all sources to all loads of a net. Neither start nor end points are specified, so have same value from all source ports to destination ports.
Device Delay
Represent the delay of all paths through a cell to the specified output port
Output Retain Delay
Represent the time required to retain the previous logic even after a change in input port.

Timing checks specify different types of limits for signal/signals the way they can change (in terms of values). Different types of limits are SETUP, HOLD, SETUPHOLD, RECOVERY, REMOVAL, SKEW, WIDTH and PERIOD. These are well known terminology in the timing, so not discussing in this blog.
Different EDA analysis tools use this information in different ways:
  • Simulation tools issue warnings about signal transitions that violate timing checks.
  • Timing analysis tools identify delay paths that might cause timing check violations and shall determine the constraints for those paths.
  • Synthesis tools use timing check values to determine if their results meet timing requirements.

Specify constraint values with critical paths in the design (PATHCONSTRAINT, PERIODCONSTRAINT, or SKEWCONSTRAINT) and provide information about the timing environment (ARRIVAL, DEPARTURE, SLACK, or WAVEFORM) in which the circuit shall operate. Constructs in this sub-clause are used in forward-annotation and not back-annotation.
Again, above constraint and environment are well know terminology in the Timing, so not discuessing in this blog.

Please see the Next Blog for few example, application of SDF constructs in different situations/circuit and how delay values are specified in a SDF and how can you interpret those values.

Wednesday, March 16, 2011

How To Read SDF (Standard Delay Format) - Part2


In the Part1 we have discussed following things:
  • Full Form of SDF
  • What is SDF?
  • Tools using this Format
  • Information in the SDF
  • Naming Convention of SDF file
  • Requirement of SDF.
Now We will discuss about the content present in the SDF file.

SDF Constructs:  Every SDF file has few KeyWord know as Constructs. Few of them are mention below.

  • Posedge and negedge identifiers
Meaning and uses of each of the Construct will be discuss one by one.

NOTE: It's not necessary that every EDA tool should use all the SDF constructs, they may not support few of the constructs. So when ever you are using a SDF file generated from any other tool, so please check the compatibility of all the SDF constructs across both the tools. As an example Primetime during "write_sdf" command does not use following SDF Constructs (out of the above list)


Syntax of SDF file:         (DELAYFILE <header section>  <cell section> )

Header Section contains all the relevant information about the SDF file like design name, sdf version, tool which is used to generate this SDF file, temperature, voltage etc. Most of the information is only for documentation purpose and are optional.
Cell Section has all the important information require for timing calculation like delay, timing constraints, timing environment and etc for a particular cell or part of the design.

Before we will discuss about these section in detail lets see a sample SDF file.

Sample SDF file:

(DELAYFILE                                                                         // Header Section
(DATE "March 15, 2011 09:00")
(PROGRAM "Timing Tool")
(VERSION "1.2a")
(VOLTAGE 1.2:1.0:0.8)
(PROCESS "best:nom:worst")
(TEMPERATURE -40:25:125)
(TIMESCALE 100 ps)

(CELL                                                                              // Cell 1
(INTERCONNECT mck b/c/clk (.6:.7:.9))
(INTERCONNECT d[0] b/c/d (.4:.5:.6))

(CELL                                                                             // Cell 2
(INSTANCE top/b/d)
(IOPATH a y (1.5:2.5:3.4) (2.5:3.6:4.7))
(IOPATH b y (1.4:2.3:3.2) (2.3:3.4:4.3))

(CELL                                                                              // Cell 3
(INSTANCE top/b/c)
(IOPATH (posedge clk) q (2:3:4) (5:6:7))
(PORT clr (2:3:4) (5:6:7))
(SETUPHOLD d (posedge clk) (3:4:5) (-1:-1:-1))
(WIDTH clk (4.4:7.5:11.3))

(CELL                                                                               // Cell4.. Cell n
. . .

Header Section:

As I have mentioned above that this section is mainly for the documentation purpose. In the Header section, sdf version is a compulsory field.
Below are the different SDF file Constructs and their details which are the parts of Header Section.

Fields/Entities of Header Section
SDF File Constructs
Sdf version
(Compulsory Field)
Identify the version of the Standard Delay Format specification
Design Name
DESIGN (Optional)
Specifies Name of the design
DATE (Optional)
Represents the Date and/or time when SDF file was generated
VENDOR (Optional)
Name of the vendor whose tools generated the SDF file
Program Name
PROGRAM (Optional)
Name of the program/tool used to generate the SDF file
Program Version
VERSION (Optional)
Tool version used to generate the SDF
Hierarchy Divider
DIVIDER (Optional)

[Default value= “.”]
Represent which characters is used in SDF to separate elements of a hierarchical path.
Allowed values are period “.” Or Slash “/”.
VOLTAGE (Optional)
Specifies the operating voltage for which the data was computed.
PROCESS (optional)
Specifies the process factor for which the data in the file was computed
TEMPERATURE (optional)
Specifies the operating temperature in degrees Celsius (centigrade)
Time Scale
Default value= 1ns
Specifies the units used for all time values in the SDF file

Lets understand it with few example. A snap shot from above example to understand most of the things.

(DATE "March 15, 2011 09:00")
(PROGRAM "Timing Tool")
(VERSION "1.2a")
(VOLTAGE 1.2:1.0:0.8)
(PROCESS "best:nom:worst")
(TEMPERATURE -40:25:125)
(TIMESCALE 100 ps)

Few more details about above parameters...

If you want to specify the timing of a specific cell present in some hierarchy, you have to specify a complete path. In that case the character you use to separate different element of the path is specified by this SDF construct.
E.g   for a AND gate present in a "top_design" with in "block1" and sub block "block2" there are 2 ways in the SDF file as per character defined in DIVIDER.
  • top_design/block1/block2/AND or
  • top_design.block1.block2.AND
(VOLTAGE 1.2:1.0:0.8)
The sequence of voltages are important here. Although not a single tool will use these information because these are only for documentation purpose. But as a consistence with the order of delay and timing check limit values in triples (minimum:typical:maximum), it should be highest voltage first and lowest voltage as last (since minimum delays usually occur at the highest supply voltage).

(TIMESCALE 100 ps)
Indicates that all time values in the file are to be multiplied by 100 picoseconds.  Means if a delay for particular path is mention like
IOPATH  (poseedge A)  Z  (2:3:4) (5:6:7))
then it means the actual delay is (0.2ns:0.3ns:0.4ns) and (0.5ns:0.6ns:0.7ns)

Please Read the Next blog for detail about the Cell Section.

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