## Index

 STA & SI Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

 Extraction & DFM Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Introduction Parasitic Interconnect Corner (RC Corner) Manufacturing Effects and Their Modeling Dielectric Layer Process Variation Other Topic

## (Effect of Transistor's Size On the Slew)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

In the Last post we have discussed - how the wire length effects the slew? Now lets discuss about the effect of size of the transistors. Also before that let's discuss few basics also.

Size of transistor:

There are 2 parameters – Width and Length, by which you can decide the size of the transistor. For a particular technology – Channel - length is almost constant. So it means Width is going to decide the size of the transistor. Below figure will refresh your memory - about which, parameter I am talking.

If you want to increase the width of the transistor, then you have 2 options. One – Just increase the Width directly, Second -connect multiple transistors in parallel in such a way that their effective impact remains same. For example – if you want to manufacture a transistor with a width of 20um and a length of 0.2um then it’s similar (not exactly the same) to having four transistors connected in parallel, each with a width of 5um and a length of 0.2um. Here I am not going to discuss the difference in both the way of representation of Layout. If you are interested then you can check any basic book of CMOS design. Below figure will refresh your memory (Note: Below figure I have copied from www.eda-utilities.com )

Now since we are talking about the transition time /transition delay /slew, we know that it depend on the capacitance and resistance. So before we start to discuss how width (means size of the transistor) impact on the transition delay, we should know what all are the capacitance associated with the transistor. Below diagram help you in that. (Note: Below figure I have copied from www.eda-utilities.com )

How the capacitance are calculated (means whole derivation and explanation), I will discuss some other time, right now I am writing/copying the value of these capacitance directly.

Note: the reference of above formulas is from the book written by “J.P.uyemura” - Cmos Logic Circuit Design Edition -2002.

Now from the above, you can see that Gate Capacitance (this gate capacitance has 3 component – Gate to Base, Gate to Source and Gate to Drain) has dependence on the Width of the Channel (W). So it means, if you increase the width, Gate Capacitance will increase and Vice-Versa.
Source and Drain Capacitance has a multiplying factor As and Ad (which is equavilant to WxLs or WxLd). It means source and drain capacitance also increases with Width of the Channel and Vice-Versa.

Now let’s talk about the Resistance. Below Resistance formula is with respect to NMOS. You can derive similar formula for PMOS also (Just replace subscript “n” with “p” J ).

Now here the Resistance is inversely proportional to Width of the Transistor.

Effect of Device Size on the Slew (transition time) and Propogation Delay.:

I can’t write in a single line the effect of size of transistor on the slew because it’s not straight forward (I know you might have doubt on my statementL). There are some other factors which we have to consider. I hope, below paragraph helps you to understand the same.

Consider the above circuit. Gate “A” is the Driving Gate and Gate “B” is the Driven Gate. If we will expand this with the actual capacitance, it will be something similar to…

• Capacitance Cgd12 is the Gate Capacitance of Driving Gate A due to overlap in M1 and M2.
• Cdb1 and Cdb2 are the diffusion capacitances due to the reverse-biased pn-junction
• Cw is the wiring capacitance (pp, fringe, and interwire) that depends on the length and width of the connecting wire. It is a function of the fanout of the gate and the distance to those gates.
• Cg3 and Cg4 are the gate capacitance of the fanout gate (Driven gate).

If we increase the size of the transistor (Width of the Transistor) it’s current carrying capability increase. Means “larger is the size of a transistor, the larger is the driving capability (the ability to source or sink current) of a transistor”. Thus a larger transistor would normally make its output transition faster (when output load is constant).  The output load of a driving gate consists of the source/drain capacitance of the driving gate, the routing capacitance of wire, and the gate capacitance of the driven gate.
The larger is the output load, the longer is the time to charge or discharge it. This would increase the transition (rise or fall) time and propagation delay.

Let me summarize few important points.
• On increasing the Size of Gate A –
• On Resistance Decreases (R - inversely proportional to W)
• Means large Driving capability (Ability to source or sink current)
• Decrease the time to charge the output load (capacitance) (Consists of  source/drain capacitance of the driving gate, the routing capacitance of wire, and the gate capacitance of the driven gate) **
• Means - Output Transition time of Gate A and Input Transition time for Gate B decreases.

I am sure you have noticed that I have marked point 3 with ** because there are terms and conditions. :)

On increasing the Size of the Gate A – Source/Drain Capacitance also increases which are the part of output load of Gate A. Means it’s going to increase the output load. That means as I have mentioned in my point no 3 – that can be possible only when S/D Capacitance of Driving gate are not dominating the rest of the Capacitance. Which is only possible when either “Net capacitance is large” (length of wire is large) or “Size of the driven gate (Gate B) is large” (which increase the Gate capacitance of GateB) or “Both should be true”.
So for Minimizing Propagation Delay, A fast Gate/Cell is required, which is only possible by
1. Keeping the output capacitance CL small (it decreases the charging and discharging time). And for this
• Minimize the area of drain pn junctions. (Decrease W)
• Minimize Interconnect capacitance. (Decrease wire/net Length)
• Avoid large fan-out. Means Minimize gate capacitance of Driven Cell. (Decrease W of Driven cell)
2. Decreasing the equivalent Resistance of the transistors
• Decrease L (For a particular technology Node It’s almost constant)
• Increase W
• But this increases pn junction area and hence CL.

So if we want to use the size of the transistor as one of the parameter to increase/decrease of the propagation/transition delay, then we should have understanding of the design and also it depends on the property of Driven Cell and Net length also.

Few last points:
1. "Delay reduces with increase in input transition and constant load capacitance".
2. "Delay increases with increase in output capacitance and constant input transition"
• Because on increasing the output capacitance – charging and discharging time will increase.

So we can say that
The delay of cell directly depends on input transition and output capacitance.

In the next post we will discuss about the effect of Threshold voltage of the Transistor on the "Transition Delay" and "Propagation Delay".

## (Effect of Wire Length On the Slew)

 STA & SI:: Chapter 2: Static Timing Analysis 2.1 2.2 2.3a 2.3b 2.3c 2.4a Timing Paths Time Borrowing Basic Concept Of Setup-Hold Basic Concept of Setup-Hold Violation Examples:S-H Time/Violation Timing Path Delay 2.4b 2.4c 2.5a 2.5b 2.6a 2.6b Interconnect Delay Models Delay - Wire Load Model Maximum Clock Frequency Calculate “Max Clock Freq”-Examples Fix Setup-Hold Violation-1 Fix Setup-Hold Violation-2 2.6c 2.7a 2.7b 2.7c 2.8 Fix Setup-Hold Violation-3 Incr/Decr Delay Method-1 Incr/Decr Delay Method-2 Incr/Decr Delay Method-3 10 ways to fix Setup-Hold Violation.

Static Timing analysis is divided into several parts:

Till now we have discussed the Ideal scenario for few of the cases. Like No Clock-to-Q delay, No Net Delay. But now we will discuss about those parameter also.

First understand/revise what are the different types or forms of Delay into a circuit.
In FFs:
• Clock to Q delay
• Propagation delay of sequential flip flop
• Time taken to charge and discharge the output load (capacitance) at Pin Q.
• Rise time and Fall time delay
Combinational Circuit:
• Cell delay
• Delay contributed by Gate itself.
• Typically defined as 50% input pin voltage to 50% output voltage.
• Usually a function of Both Output Loading and Input Transition time.
• Can be divide into propagation delay and transition delay.
• Propagation delay is the time from input transition to completion of a specific % (e.g 10%) of the output transition.
• Propagation delay is function of output loading and input transition time.
• Transition Delay is the time for an output pin to change the stage.
• Transition delay is function of capacitance at the output pin and can also be a function of input transition time.
• Time taken to charge and discharge the output load (capacitance) of the Cell output.
Net Delay:
• RC delay.
• Long wire has more delay in comparison to short wire.
• More coupling means more delay.

Now we will discuss different techniques to increase or decrease the delay in the design. We will also discuss the basics of different techniques, which will help us to understand why we are using any particular technique.

Now we have to see what best we can do to remove these violations or as explained earlier – How can we increase or decrease the delay of the clock or data path in the design. If I will ask you, then might be you can tell me 10 ways to do so. But I don’t want to explain in that way. Let’s start one by one with basics and then in the last I will brief all those points.

Let’s talk about the Transition delay first. There are 2 types of transition delays. Rise Delay and Fall delay. In terms of definition

• Rise Time Delay (tr):  The time required for a signal to transition from 10% of its maximum value to 90% of its maximum value.
• Fall Time Delay (tf):  The time required for a signal to transition from 90% of its maximum value to 10% of its maximum value.

Basically these times (rise time and fall time) are related to the Capacitance Charging and Discharging time.
So when capacitance is charging just because of any change in the input voltage then time taken by capacitance to reach from 10% to 90% of maximum value is known as rise time. Since this time (rise time) is going to introduce the delay in the circuit in comparison to the Ideal scenario (Capacitance charging time is Zero – It can charge instantly), it’s known as Rise Time Delay also.
Similarly, during the discharging of the capacitance from 90% to 10% of its maximum value, it’s going to add one more delay – known as Fall Time Delay.
Following figure is just an example of rise time and fall time.
Note: Transition time is also known as Slew.

So we can say that Capacitance (and the associated Resistance) is the culprit. J And if we can play with capacitance/resistance, we can increase and decrease Transition Delay.

Now, whenever we are talking about any signal which is changing its state from “0” to “1” or from “1” to “0”, we are sure that it can’t be ideal (Ideal means its changing its state in Zero “0” time). If you have any doubt on this statement then defiantly I have to ask you to read some very basic books once again. J
Every “state changing signal” has a Slew Number (common name of Rise time and Fall time) associated with itself at any given point of time.

#### Effect of Wire length on the Slew (transition time):

In the below figure you can observe, how the step waveform (consider this as ideal one) degrades from the start to the end of the wire (color coding can help you to understand) and this is resulting a considerable amount of delay for long wires. That means if wire length is less, then degradation of waveform be less, means less effective delay and Vice-versa. We can conclude from this-
“If we want to increase the delay- we can increase the wire length and vice versa”

More simulation results you can see from this picture… (Following picture I have copied from book “DEEP SUBMICRON CMOS DESIGN” written by E.Sicard, S. Delmas-Bendhia )

I am sure you can cross question me that why this degradation is happing. Simple Ans is  - you can model a wire into a series of Resistance and Capacitance network. For more detail please refer following post Interconnect Delay Models.
Note: This delay is also known as Net delay/Wire Delay/Interconnect Delay.

In the next post we will discuss about the effect of Size of the Transistor on the "Transition Delay" and "Propagation Delay".